[llvm-commits] [llvm] r70440 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/ExecutionEngine/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/ lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/ lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/Mips...
Evan Cheng
evan.cheng at apple.com
Wed Apr 29 17:44:03 PDT 2009
Please remove CodeGenOpt::Size. Optimizing for size is a different
knob from the general codegen optimization level. We place function
notes on function declarations that indicate a function should be
optimized for size.
Also, why do we need CodeGenOpt::Default in addition to
CodeGenOpt::One Two, and Aggressive? How do you expect
CodeGenOpt::Default be used? Why not just have "None", "Default",
"Aggressive"?
Evan
On Apr 29, 2009, at 4:29 PM, Bill Wendling wrote:
> Author: void
> Date: Wed Apr 29 18:29:43 2009
> New Revision: 70440
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70440&view=rev
> Log:
> Instead of passing in an unsigned value for the optimization level,
> use an enum,
> which better identifies what the optimization is doing. And is more
> flexible for
> future uses.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
> llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
> llvm/trunk/include/llvm/Target/TargetMachine.h
> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
> llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
> llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
> llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
> llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
> llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
> llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
> llvm/trunk/lib/Target/ARM/ARM.h
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> llvm/trunk/lib/Target/Alpha/Alpha.h
> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
> llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> llvm/trunk/lib/Target/CBackend/CBackend.cpp
> llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> llvm/trunk/lib/Target/CellSPU/SPU.h
> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
> llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> llvm/trunk/lib/Target/IA64/IA64.h
> llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
> llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
> llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
> llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> llvm/trunk/lib/Target/Mips/Mips.h
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> llvm/trunk/lib/Target/PIC16/PIC16.h
> llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
> llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
> llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
> llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
> llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> llvm/trunk/lib/Target/PowerPC/PPC.h
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
> llvm/trunk/lib/Target/Sparc/Sparc.h
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
> llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> llvm/trunk/lib/Target/X86/X86.h
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.h
> llvm/trunk/lib/Target/XCore/XCore.h
> llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> llvm/trunk/tools/llc/llc.cpp
> llvm/trunk/tools/lli/lli.cpp
> llvm/trunk/tools/lto/LTOCodeGenerator.cpp
> llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Apr 29 18:29:43
> 2009
> @@ -16,9 +16,10 @@
> #ifndef LLVM_CODEGEN_ASMPRINTER_H
> #define LLVM_CODEGEN_ASMPRINTER_H
>
> +#include "llvm/ADT/DenseMap.h"
> #include "llvm/CodeGen/MachineFunctionPass.h"
> #include "llvm/Support/DataTypes.h"
> -#include "llvm/ADT/DenseMap.h"
> +#include "llvm/Target/TargetMachine.h"
> #include <set>
>
> namespace llvm {
> @@ -66,7 +67,7 @@
> std::set<const GlobalValue*> ExtWeakSymbols;
>
> /// OptLevel - Generating code at a specific optimization level.
> - unsigned OptLevel;
> + CodeGenOpt::Level OptLevel;
> public:
> /// Output stream on which we're printing assembly code.
> ///
> @@ -111,7 +112,7 @@
>
> protected:
> explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL, bool V);
> + const TargetAsmInfo *T, CodeGenOpt::Level
> OL, bool V);
>
> public:
> virtual ~AsmPrinter();
>
> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Wed Apr 29
> 18:29:43 2009
> @@ -21,6 +21,7 @@
> #define LLVM_CODEGEN_DWARFWRITER_H
>
> #include "llvm/Pass.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -81,7 +82,7 @@
> void EndFunction(MachineFunction *MF);
>
> /// ValidDebugInfo - Return true if V represents valid debug info
> value.
> - bool ValidDebugInfo(Value *V, unsigned OptLevel);
> + bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
>
> /// RecordSourceLine - Register a source line with debug info.
> Returns a
> /// unique label ID used to generate a label and provide
> correspondence to
>
> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> (original)
> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Wed
> Apr 29 18:29:43 2009
> @@ -18,6 +18,7 @@
> #include "llvm/CodeGen/Passes.h"
> #include "llvm/CodeGen/SchedulerRegistry.h"
> #include "llvm/CodeGen/GCs.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace {
> struct ForceCodegenLinking {
> @@ -42,11 +43,11 @@
> llvm::linkOcamlGC();
> llvm::linkShadowStackGC();
>
> - (void) llvm::createBURRListDAGScheduler(NULL, 3);
> - (void) llvm::createTDRRListDAGScheduler(NULL, 3);
> - (void) llvm::createTDListDAGScheduler(NULL, 3);
> - (void) llvm::createFastDAGScheduler(NULL, 3);
> - (void) llvm::createDefaultScheduler(NULL, 3);
> + (void) llvm::createBURRListDAGScheduler(NULL,
> llvm::CodeGenOpt::Default);
> + (void) llvm::createTDRRListDAGScheduler(NULL,
> llvm::CodeGenOpt::Default);
> + (void) llvm::createTDListDAGScheduler(NULL,
> llvm::CodeGenOpt::Default);
> + (void) llvm::createFastDAGScheduler(NULL,
> llvm::CodeGenOpt::Default);
> + (void) llvm::createDefaultScheduler(NULL,
> llvm::CodeGenOpt::Default);
>
> }
> } ForceCodegenLinking; // Force link by creating a global
> definition.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Wed Apr 29
> 18:29:43 2009
> @@ -16,6 +16,7 @@
> #define LLVM_CODEGENSCHEDULERREGISTRY_H
>
> #include "llvm/CodeGen/MachinePassRegistry.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -32,7 +33,8 @@
>
> class RegisterScheduler : public MachinePassRegistryNode {
> public:
> - typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
> (SelectionDAGISel*, unsigned);
> + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
> + CodeGenOpt::Level);
>
> static MachinePassRegistry Registry;
>
> @@ -64,27 +66,27 @@
> /// createBURRListDAGScheduler - This creates a bottom up register
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> /// createTDRRListDAGScheduler - This creates a top down register
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> /// createTDListDAGScheduler - This creates a top-down list
> scheduler with
> /// a hazard recognizer.
> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> /// createFastDAGScheduler - This creates a "fast" scheduler.
> ///
> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> /// createDefaultScheduler - This creates an instruction scheduler
> appropriate
> /// for the target.
> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> } // end namespace llvm
>
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Apr 29
> 18:29:43 2009
> @@ -20,7 +20,7 @@
> #include "llvm/ADT/FoldingSet.h"
> #include "llvm/ADT/StringMap.h"
> #include "llvm/CodeGen/SelectionDAGNodes.h"
> -
> +#include "llvm/Target/TargetMachine.h"
> #include <cassert>
> #include <vector>
> #include <map>
> @@ -30,7 +30,6 @@
>
> class AliasAnalysis;
> class TargetLowering;
> -class TargetMachine;
> class MachineModuleInfo;
> class DwarfWriter;
> class MachineFunction;
> @@ -202,7 +201,8 @@
> /// certain types of nodes together, or eliminating superfluous
> nodes. The
> /// Level argument controls whether Combine is allowed to produce
> nodes and
> /// types that are illegal on the target.
> - void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned
> OptLevel);
> + void Combine(CombineLevel Level, AliasAnalysis &AA,
> + CodeGenOpt::Level OptLevel);
>
> /// LegalizeTypes - This transforms the SelectionDAG into a
> SelectionDAG that
> /// only uses types natively supported by the target. Returns
> "true" if it
> @@ -218,7 +218,7 @@
> ///
> /// Note that this is an involved process that may invalidate
> pointers into
> /// the graph.
> - void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
> + void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level
> OptLevel);
>
> /// RemoveDeadNodes - This method deletes all unreachable nodes in
> the
> /// SelectionDAG.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Apr 29
> 18:29:43 2009
> @@ -51,10 +51,11 @@
> MachineBasicBlock *BB;
> AliasAnalysis *AA;
> GCFunctionInfo *GFI;
> - unsigned OptLevel;
> + CodeGenOpt::Level OptLevel;
> static char ID;
>
> - explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
> + explicit SelectionDAGISel(TargetMachine &tm,
> + CodeGenOpt::Level OL =
> CodeGenOpt::Default);
> virtual ~SelectionDAGISel();
>
> TargetLowering &getTargetLowering() { return TLI; }
>
> Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
> (original)
> +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed
> Apr 29 18:29:43 2009
> @@ -18,8 +18,9 @@
> #include <vector>
> #include <map>
> #include <string>
> -#include "llvm/System/Mutex.h"
> #include "llvm/ADT/SmallVector.h"
> +#include "llvm/System/Mutex.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -84,7 +85,7 @@
> // libraries, the JIT and Interpreter set these functions to ctor
> pointers
> // at startup time if they are linked in.
> typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
> - unsigned OptLevel);
> + CodeGenOpt::Level OptLevel);
> static EECtorFn JITCtor, InterpCtor;
>
> /// LazyFunctionCreator - If an unknown function is needed, this
> function
> @@ -114,7 +115,8 @@
> static ExecutionEngine *create(ModuleProvider *MP,
> bool ForceInterpreter = false,
> std::string *ErrorStr = 0,
> - unsigned OptLevel = 3);
> + CodeGenOpt::Level OptLevel =
> + CodeGenOpt::Default);
>
> /// create - This is the factory method for creating an execution
> engine which
> /// is appropriate for the current machine. This takes ownership
> of the
> @@ -127,10 +129,9 @@
> static ExecutionEngine *createJIT(ModuleProvider *MP,
> std::string *ErrorStr = 0,
> JITMemoryManager *JMM = 0,
> - unsigned OptLevel = 3);
> -
> -
> -
> + CodeGenOpt::Level OptLevel =
> + CodeGenOpt::Default);
> +
> /// addModuleProvider - Add a ModuleProvider to the list of
> modules that we
> /// can JIT from. Note that this takes ownership of the
> ModuleProvider: when
> /// the ExecutionEngine is destroyed, it destroys the MP as well.
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -68,6 +68,19 @@
> };
> }
>
> +// Code generation optimization level.
> +namespace CodeGenOpt {
> + enum Level {
> + Default,
> + None,
> + One,
> + Two,
> + Size,
> + Aggressive,
> + LTO
> + };
> +}
> +
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> ///
> /// TargetMachine - Primary interface to the complete machine
> description for
> @@ -213,7 +226,7 @@
> virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
> raw_ostream &,
> CodeGenFileType,
> - unsigned /* OptLevel
> */) {
> + CodeGenOpt::Level) {
> return FileModel::None;
> }
>
> @@ -223,7 +236,7 @@
> ///
> virtual bool addPassesToEmitFileFinish(PassManagerBase &,
> MachineCodeEmitter *,
> - unsigned /* OptLevel */) {
> + CodeGenOpt::Level) {
> return true;
> }
>
> @@ -235,7 +248,7 @@
> ///
> virtual bool addPassesToEmitMachineCode(PassManagerBase &,
> MachineCodeEmitter &,
> - unsigned /* OptLevel */) {
> + CodeGenOpt::Level) {
> return true;
> }
>
> @@ -245,7 +258,7 @@
> virtual bool WantsWholeFile() const { return false; }
> virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
> CodeGenFileType,
> - unsigned /* OptLevel */) {
> + CodeGenOpt::Level) {
> return true;
> }
> };
> @@ -260,13 +273,13 @@
> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
> for
> /// both emitting to assembly files or machine code output.
> ///
> - bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*
> OptLevel */);
> + bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
>
> public:
>
> /// addPassesToEmitFile - Add passes to the specified pass manager
> to get the
> /// specified file emitted. Typically this will involve several
> steps of code
> - /// generation. If OptLevel is 0, the code generator should emit
> code as fast
> + /// generation. If OptLevel is None, the code generator should
> emit code as fast
> /// as possible, though the generated code may be less efficient.
> This method
> /// should return FileModel::Error if emission of this file type
> is not
> /// supported.
> @@ -278,7 +291,7 @@
> virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
> raw_ostream &Out,
> CodeGenFileType
> FileType,
> - unsigned OptLevel);
> + CodeGenOpt::Level);
>
> /// addPassesToEmitFileFinish - If the passes to emit the
> specified file had
> /// to be split up (e.g., to add an object writer pass), this
> method can be
> @@ -286,7 +299,7 @@
> ///
> virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
> MachineCodeEmitter *MCE,
> - unsigned OptLevel);
> + CodeGenOpt::Level);
>
> /// addPassesToEmitMachineCode - Add passes to the specified pass
> manager to
> /// get machine code emitted. This uses a MachineCodeEmitter
> object to handle
> @@ -296,21 +309,21 @@
> ///
> virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
> MachineCodeEmitter &MCE,
> - unsigned OptLevel);
> + CodeGenOpt::Level);
>
> /// Target-Independent Code Generator Pass Configuration Options.
>
> /// addInstSelector - This method should add any "last minute"
> LLVM->LLVM
> /// passes, then install an instruction selector pass, which
> converts from
> /// LLVM code to machine instructions.
> - virtual bool addInstSelector(PassManagerBase &, unsigned /*
> OptLevel */) {
> + virtual bool addInstSelector(PassManagerBase &,
> CodeGenOpt::Level) {
> return true;
> }
>
> /// addPreRegAllocPasses - This method may be implemented by
> targets that want
> /// to run passes immediately before register allocation. This
> should return
> /// true if -print-machineinstrs should print after these passes.
> - virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*
> OptLevel */) {
> + virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
> return false;
> }
>
> @@ -318,14 +331,14 @@
> /// want to run passes after register allocation but before prolog-
> epilog
> /// insertion. This should return true if -print-machineinstrs
> should print
> /// after these passes.
> - virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*
> OptLevel */) {
> + virtual bool addPostRegAlloc(PassManagerBase &,
> CodeGenOpt::Level) {
> return false;
> }
>
> /// addPreEmitPass - This pass may be implemented by targets that
> want to run
> /// passes immediately before machine code is emitted. This
> should return
> /// true if -print-machineinstrs should print out the code after
> the passes.
> - virtual bool addPreEmitPass(PassManagerBase &, unsigned /*
> OptLevel */) {
> + virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
> return false;
> }
>
> @@ -333,7 +346,7 @@
> /// addAssemblyEmitter - This pass should be overridden by the
> target to add
> /// the asmprinter, if asm emission is supported. If this is not
> supported,
> /// 'true' should be returned.
> - virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*
> OptLevel */,
> + virtual bool addAssemblyEmitter(PassManagerBase &,
> CodeGenOpt::Level,
> bool /* VerboseAsmDefault */,
> raw_ostream &) {
> return true;
> }
> @@ -341,7 +354,7 @@
> /// addCodeEmitter - This pass should be overridden by the target
> to add a
> /// code emitter, if supported. If this is not supported, 'true'
> should be
> /// returned. If DumpAsm is true, the generated assembly is
> printed to cerr.
> - virtual bool addCodeEmitter(PassManagerBase &, unsigned /*
> OptLevel */,
> + virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
> bool /*DumpAsm*/, MachineCodeEmitter
> &) {
> return true;
> }
> @@ -350,7 +363,7 @@
> /// a code emitter (without setting flags), if supported. If this
> is not
> /// supported, 'true' should be returned. If DumpAsm is true, the
> generated
> /// assembly is printed to cerr.
> - virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*
> OptLevel */,
> + virtual bool addSimpleCodeEmitter(PassManagerBase &,
> CodeGenOpt::Level,
> bool /*DumpAsm*/,
> MachineCodeEmitter &) {
> return true;
> }
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Apr 29
> 18:29:43 2009
> @@ -27,7 +27,6 @@
> #include "llvm/Target/TargetAsmInfo.h"
> #include "llvm/Target/TargetData.h"
> #include "llvm/Target/TargetLowering.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetOptions.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/ADT/SmallPtrSet.h"
> @@ -42,7 +41,7 @@
>
> char AsmPrinter::ID = 0;
> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
> - const TargetAsmInfo *T, unsigned OL, bool
> VDef)
> + const TargetAsmInfo *T, CodeGenOpt::Level
> OL, bool VDef)
> : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
> TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
> IsInTextSection(false)
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Apr 29
> 18:29:43 2009
> @@ -3351,7 +3351,7 @@
> }
>
> /// ValidDebugInfo - Return true if V represents valid debug info
> value.
> - bool ValidDebugInfo(Value *V, unsigned OptLevel) {
> + bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
> if (!V)
> return false;
>
> @@ -3393,7 +3393,7 @@
> case DW_TAG_lexical_block:
> /// FIXME. This interfers with the qualitfy of generated code
> when
> /// during optimization.
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> return false;
> default:
> break;
> @@ -4731,7 +4731,7 @@
> }
>
> /// ValidDebugInfo - Return true if V represents valid debug info
> value.
> -bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
> +bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level
> OptLevel) {
> return DD && DD->ValidDebugInfo(V, OptLevel);
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Apr 29 18:29:43
> 2009
> @@ -55,7 +55,7 @@
> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
> raw_ostream &Out,
> CodeGenFileType FileType,
> - unsigned OptLevel) {
> + CodeGenOpt::Level OptLevel) {
> // Add common CodeGen passes.
> if (addCommonCodeGenPasses(PM, OptLevel))
> return FileModel::Error;
> @@ -69,7 +69,7 @@
> if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
> PM.add(createMachineFunctionPrinterPass(cerr));
>
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> PM.add(createLoopAlignerPass());
>
> switch (FileType) {
> @@ -94,7 +94,7 @@
> /// finish up adding passes to emit the file, if necessary.
> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
> MachineCodeEmitter
> *MCE,
> - unsigned
> OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> if (MCE)
> addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>
> @@ -114,7 +114,7 @@
> ///
> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase
> &PM,
>
> MachineCodeEmitter &MCE,
> - unsigned
> OptLevel) {
> +
> CodeGenOpt::Level OptLevel) {
> // Add common CodeGen passes.
> if (addCommonCodeGenPasses(PM, OptLevel))
> return true;
> @@ -132,15 +132,15 @@
> return false; // success!
> }
>
> -/// addCommonCodeGenPasses - Add standard LLVM codegen passes used
> for
> -/// both emitting to assembly files or machine code output.
> +/// addCommonCodeGenPasses - Add standard LLVM codegen passes used
> for both
> +/// emitting to assembly files or machine code output.
> ///
> bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> // Standard LLVM-Level Passes.
>
> // Run loop strength reduction before anything else.
> - if (OptLevel != 0) {
> + if (OptLevel != CodeGenOpt::None) {
> PM.add(createLoopStrengthReducePass(getTargetLowering()));
> if (PrintLSR)
> PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",
> &errs()));
> @@ -154,7 +154,7 @@
> // Make sure that no unreachable blocks are instruction selected.
> PM.add(createUnreachableBlockEliminationPass());
>
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> PM.add(createCodeGenPreparePass(getTargetLowering()));
>
> PM.add(createStackProtectorPass(getTargetLowering()));
> @@ -168,7 +168,7 @@
>
> // Enable FastISel with -fast, but allow that to be overridden.
> if (EnableFastISelOption == cl::BOU_TRUE ||
> - (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
> + (OptLevel == CodeGenOpt::None && EnableFastISelOption !=
> cl::BOU_FALSE))
> EnableFastISel = true;
>
> // Ask the target for an isel.
> @@ -179,7 +179,7 @@
> if (PrintMachineCode)
> PM.add(createMachineFunctionPrinterPass(cerr));
>
> - if (OptLevel != 0) {
> + if (OptLevel != CodeGenOpt::None) {
> PM.add(createMachineLICMPass());
> PM.add(createMachineSinkingPass());
> }
> @@ -192,7 +192,7 @@
> PM.add(createRegisterAllocator());
>
> // Perform stack slot coloring.
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> PM.add(createStackSlotColoringPass());
>
> if (PrintMachineCode) // Print the register-allocated code
> @@ -217,7 +217,7 @@
> PM.add(createMachineFunctionPrinterPass(cerr));
>
> // Second pass scheduler.
> - if (OptLevel != 0 && !DisablePostRAScheduler) {
> + if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
> PM.add(createPostRAScheduler());
>
> if (PrintMachineCode)
> @@ -225,7 +225,7 @@
> }
>
> // Branch folding must be run after regalloc and prolog/epilog
> insertion.
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>
> if (PrintMachineCode)
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 29
> 18:29:43 2009
> @@ -57,7 +57,7 @@
> SelectionDAG &DAG;
> const TargetLowering &TLI;
> CombineLevel Level;
> - unsigned OptLevel;
> + CodeGenOpt::Level OptLevel;
> bool LegalOperations;
> bool LegalTypes;
>
> @@ -254,7 +254,7 @@
> }
>
> public:
> - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
> + DAGCombiner(SelectionDAG &D, AliasAnalysis &A,
> CodeGenOpt::Level OL)
> : DAG(D),
> TLI(D.getTargetLoweringInfo()),
> Level(Unrestricted),
> @@ -4784,7 +4784,7 @@
> SDValue Ptr = LD->getBasePtr();
>
> // Try to infer better alignment information than the load already
> has.
> - if (OptLevel != 0 && LD->isUnindexed()) {
> + if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
> if (unsigned Align = InferAlignment(Ptr, DAG)) {
> if (Align > LD->getAlignment())
> return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc
> (),
> @@ -4904,7 +4904,7 @@
> SDValue Ptr = ST->getBasePtr();
>
> // Try to infer better alignment information than the store
> already has.
> - if (OptLevel != 0 && ST->isUnindexed()) {
> + if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
> if (unsigned Align = InferAlignment(Ptr, DAG)) {
> if (Align > ST->getAlignment())
> return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
> @@ -6093,7 +6093,7 @@
> // SelectionDAG::Combine - This is the entry point for the file.
> //
> void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
> - unsigned OptLevel) {
> + CodeGenOpt::Level OptLevel) {
> /// run - This is the main entry point to this class.
> ///
> DAGCombiner(*this, AA, OptLevel).Run(Level);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Apr 29
> 18:29:43 2009
> @@ -327,7 +327,7 @@
> default: break;
> case Intrinsic::dbg_stoppoint: {
> DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
> - if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
> + if (DW && DW->ValidDebugInfo(SPI->getContext(),
> CodeGenOpt::None)) {
> DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
> std::string Dir, FN;
> unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
> @@ -344,7 +344,7 @@
> }
> case Intrinsic::dbg_region_start: {
> DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
> - if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
> + if (DW && DW->ValidDebugInfo(RSI->getContext(),
> CodeGenOpt::None)) {
> unsigned ID =
> DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext
> ()));
> const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
> @@ -354,7 +354,7 @@
> }
> case Intrinsic::dbg_region_end: {
> DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
> - if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
> + if (DW && DW->ValidDebugInfo(REI->getContext(),
> CodeGenOpt::None)) {
> unsigned ID = 0;
> DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
> if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction
> ())) {
> @@ -380,7 +380,7 @@
> DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
> Value *SP = FSI->getSubprogram();
>
> - if (DW->ValidDebugInfo(SP, 0)) {
> + if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
> // llvm.dbg.func.start implicitly defines a dbg_stoppoint
> which is what
> // (most?) gdb expects.
> DebugLoc PrevLoc = DL;
> @@ -425,7 +425,7 @@
> case Intrinsic::dbg_declare: {
> DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
> Value *Variable = DI->getVariable();
> - if (DW && DW->ValidDebugInfo(Variable, 0)) {
> + if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
> // Determine the address of the declared object.
> Value *Address = DI->getAddress();
> if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29
> 18:29:43 2009
> @@ -55,7 +55,7 @@
> class VISIBILITY_HIDDEN SelectionDAGLegalize {
> TargetLowering &TLI;
> SelectionDAG &DAG;
> - unsigned OptLevel;
> + CodeGenOpt::Level OptLevel;
> bool TypesNeedLegalizing;
>
> // Libcall insertion helpers.
> @@ -139,7 +139,7 @@
>
> public:
> explicit SelectionDAGLegalize(SelectionDAG &DAG, bool
> TypesNeedLegalizing,
> - unsigned ol);
> + CodeGenOpt::Level ol);
>
> /// getTypeAction - Return how we should legalize values of this
> type, either
> /// it is already legal or we need to expand it into multiple
> registers of
> @@ -350,7 +350,7 @@
> }
>
> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
> - bool types, unsigned ol)
> + bool types,
> CodeGenOpt::Level ol)
> : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
> TypesNeedLegalizing(types), ValueTypeActions
> (TLI.getValueTypeActions()) {
> assert(MVT::LAST_VALUETYPE <= 32 &&
> @@ -1276,7 +1276,7 @@
> unsigned Line = DSP->getLine();
> unsigned Col = DSP->getColumn();
>
> - if (OptLevel == 0) {
> + if (OptLevel == CodeGenOpt::None) {
> // A bit self-referential to have DebugLoc on Debug_Loc
> nodes, but it
> // won't hurt anything.
> if (useDEBUG_LOC) {
> @@ -8571,7 +8571,8 @@
>
> // SelectionDAG::Legalize - This is the entry point for the file.
> //
> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned
> OptLevel) {
> +void SelectionDAG::Legalize(bool TypesNeedLegalizing,
> + CodeGenOpt::Level OptLevel) {
> /// run - This is the main entry point to this class.
> ///
> SelectionDAGLegalize(*this, TypesNeedLegalizing,
> OptLevel).LegalizeDAG();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Wed Apr
> 29 18:29:43 2009
> @@ -630,6 +630,6 @@
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createFastDAGScheduler(SelectionDAGISel *IS,
> CodeGenOpt::Level) {
> return new ScheduleDAGFast(*IS->MF);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Apr
> 29 18:29:43 2009
> @@ -261,7 +261,7 @@
> /// new hazard recognizer. This scheduler takes ownership of the
> hazard
> /// recognizer and deletes it when done.
> ScheduleDAGSDNodes *
> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
> CodeGenOpt::Level) {
> return new ScheduleDAGList(*IS->MF,
> new LatencyPriorityQueue(),
> IS->CreateTargetHazardRecognizer());
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed
> Apr 29 18:29:43 2009
> @@ -1505,7 +1505,7 @@
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
> CodeGenOpt::Level) {
> const TargetMachine &TM = IS->TM;
> const TargetInstrInfo *TII = TM.getInstrInfo();
> const TargetRegisterInfo *TRI = TM.getRegisterInfo();
> @@ -1519,7 +1519,7 @@
> }
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
> CodeGenOpt::Level) {
> const TargetMachine &TM = IS->TM;
> const TargetInstrInfo *TII = TM.getInstrInfo();
> const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed
> Apr 29 18:29:43 2009
> @@ -45,7 +45,6 @@
> #include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/Target/TargetIntrinsicInfo.h"
> #include "llvm/Target/TargetLowering.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetOptions.h"
> #include "llvm/Support/Compiler.h"
> #include "llvm/Support/CommandLine.h"
> @@ -335,7 +334,8 @@
> DwarfWriter *DW = DAG.getDwarfWriter();
> DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>
> - if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
> + if (DW && DW->ValidDebugInfo(SPI->getContext(),
> + CodeGenOpt::Default)) {
> DICompileUnit CU(cast<GlobalVariable>(SPI->getContext
> ()));
> std::string Dir, FN;
> unsigned SrcFile = DW->getOrCreateSourceID
> (CU.getDirectory(Dir),
> @@ -354,7 +354,7 @@
> DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
> Value *SP = FSI->getSubprogram();
>
> - if (DW->ValidDebugInfo(SP, false)) {
> + if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
> DISubprogram Subprogram(cast<GlobalVariable>(SP));
> DICompileUnit CU(Subprogram.getCompileUnit());
> std::string Dir, FN;
> @@ -3899,7 +3899,7 @@
> DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
> if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
> MachineFunction &MF = DAG.getMachineFunction();
> - if (OptLevel == 0)
> + if (OptLevel == CodeGenOpt::None)
> DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
> SPI.getLine(),
> SPI.getColumn(),
> @@ -3940,7 +3940,7 @@
> && strcmp(SPName.c_str(), MF.getFunction()->getNameStart
> ())) {
> // This is end of inlined function. Debugging information
> for
> // inlined function is not handled yet (only supported by
> FastISel).
> - if (OptLevel == 0) {
> + if (OptLevel == CodeGenOpt::None) {
> unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
> if (ID != 0)
> // Returned ID is 0 if this is unbalanced "end of inlined
> @@ -3968,7 +3968,7 @@
> Value *SP = FSI.getSubprogram();
> if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
> MachineFunction &MF = DAG.getMachineFunction();
> - if (OptLevel == 0) {
> + if (OptLevel == CodeGenOpt::None) {
> // llvm.dbg.func.start implicitly defines a dbg_stoppoint
> which is what
> // (most?) gdb expects.
> DebugLoc PrevLoc = CurDebugLoc;
> @@ -4039,7 +4039,7 @@
> return 0;
> }
> case Intrinsic::dbg_declare: {
> - if (OptLevel == 0) {
> + if (OptLevel == CodeGenOpt::None) {
> DwarfWriter *DW = DAG.getDwarfWriter();
> DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
> Value *Variable = DI.getVariable();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Wed Apr
> 29 18:29:43 2009
> @@ -23,6 +23,7 @@
> #include "llvm/CodeGen/SelectionDAGNodes.h"
> #include "llvm/CodeGen/ValueTypes.h"
> #include "llvm/Support/CallSite.h"
> +#include "llvm/Target/TargetMachine.h"
> #include <vector>
> #include <set>
>
> @@ -357,13 +358,14 @@
>
> /// OptLevel - What optimization level we're generating code for.
> ///
> - unsigned OptLevel;
> + CodeGenOpt::Level OptLevel;
>
> /// GFI - Garbage collection metadata for the function.
> GCFunctionInfo *GFI;
>
> SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
> - FunctionLoweringInfo &funcinfo, unsigned ol)
> + FunctionLoweringInfo &funcinfo,
> + CodeGenOpt::Level ol)
> : CurDebugLoc(DebugLoc::getUnknownLoc()),
> TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr
> 29 18:29:43 2009
> @@ -136,10 +136,10 @@
> /// createDefaultScheduler - This creates an instruction scheduler
> appropriate
> /// for the target.
> ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> const TargetLowering &TLI = IS->getTargetLowering();
>
> - if (OptLevel == 0)
> + if (OptLevel == CodeGenOpt::None)
> return createFastDAGScheduler(IS, OptLevel);
> if (TLI.getSchedulingPreference() ==
> TargetLowering::SchedulingForLatency)
> return createTDListDAGScheduler(IS, OptLevel);
> @@ -262,7 +262,7 @@
> // SelectionDAGISel code
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
> CodeGenOpt::Level OL) :
> FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
> FuncInfo(new FunctionLoweringInfo(TLI)),
> CurDAG(new SelectionDAG(TLI, *FuncInfo)),
> @@ -645,7 +645,7 @@
>
> if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> ComputeLiveOutVRegInfo();
>
> // Third, instruction select all of the operations to machine
> code, adding the
>
> Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -383,7 +383,7 @@
> ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
> bool ForceInterpreter,
> std::string *ErrorStr,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> ExecutionEngine *EE = 0;
>
> // Make sure we can resolve symbols in the program as well. The
> zero arg
>
> Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp Wed
> Apr 29 18:29:43 2009
> @@ -114,7 +114,7 @@
>
> int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
> LLVMModuleProviderRef MP,
> - unsigned OptLevel,
> + CodeGenOpt::Level OptLevel,
> char **OutError) {
> std::string Error;
> if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP),
> &Error, 0,
>
> Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed
> Apr 29 18:29:43 2009
> @@ -37,7 +37,7 @@
> /// create - Create a new interpreter object. This can never fail.
> ///
> ExecutionEngine *Interpreter::create(ModuleProvider *MP,
> std::string* ErrStr,
> - unsigned OptLevel /*unused*/) {
> + CodeGenOpt::Level OptLevel /
> *unused*/) {
> // Tell this ModuleProvide to materialize and release the module
> if (!MP->materializeModule(ErrStr))
> // We got an error, just return 0
>
> Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Wed Apr
> 29 18:29:43 2009
> @@ -108,7 +108,7 @@
> /// create - Create an interpreter ExecutionEngine. This can never
> fail.
> ///
> static ExecutionEngine *create(ModuleProvider *M, std::string
> *ErrorStr = 0,
> - unsigned OptLevel /*unused*/ = 3);
> + CodeGenOpt::Level =
> CodeGenOpt::Default);
>
> /// run - Start execution with the specified function and arguments.
> ///
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Wed Apr 29 18:29:43
> 2009
> @@ -196,7 +196,7 @@
> ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
> std::string *ErrorStr,
> JITMemoryManager *JMM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
> if (!EE) return 0;
>
> @@ -207,7 +207,7 @@
> }
>
> JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
> - JITMemoryManager *JMM, unsigned OptLevel)
> + JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
> : ExecutionEngine(MP), TM(tm), TJI(tji) {
> setTargetData(TM.getTargetData());
>
> @@ -272,7 +272,7 @@
>
> // Turn the machine code intermediate representation into bytes
> in memory
> // that may be executed.
> - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> + if (TM.addPassesToEmitMachineCode(PM, *MCE,
> CodeGenOpt::Default)) {
> cerr << "Target does not support machine code emission!\n";
> abort();
> }
> @@ -305,7 +305,7 @@
>
> // Turn the machine code intermediate representation into bytes
> in memory
> // that may be executed.
> - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> + if (TM.addPassesToEmitMachineCode(PM, *MCE,
> CodeGenOpt::Default)) {
> cerr << "Target does not support machine code emission!\n";
> abort();
> }
> @@ -337,7 +337,7 @@
>
> // Turn the machine code intermediate representation into bytes
> in memory
> // that may be executed.
> - if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> + if (TM.addPassesToEmitMachineCode(PM, *MCE,
> CodeGenOpt::Default)) {
> cerr << "Target does not support machine code emission!\n";
> abort();
> }
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Wed Apr 29 18:29:43 2009
> @@ -55,7 +55,7 @@
> JITState *jitstate;
>
> JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
> - JITMemoryManager *JMM, unsigned OptLevel);
> + JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
> public:
> ~JIT();
>
> @@ -71,7 +71,8 @@
> /// for the current target. Otherwise, return null.
> ///
> static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
> - unsigned OptLevel = 3) {
> + CodeGenOpt::Level OptLevel =
> + CodeGenOpt::Default) {
> return createJIT(MP, Err, 0, OptLevel);
> }
>
> @@ -148,7 +149,8 @@
> MachineCodeEmitter *getCodeEmitter() const { return MCE; }
>
> static ExecutionEngine *createJIT(ModuleProvider *MP, std::string
> *Err,
> - JITMemoryManager *JMM, unsigned
> OptLevel);
> + JITMemoryManager *JMM,
> + CodeGenOpt::Level OptLevel);
>
> private:
> static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager
> *JMM);
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp Wed Apr 29
> 18:29:43 2009
> @@ -42,7 +42,8 @@
> /// available for the current target. Otherwise, return null.
> ///
> ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string
> *ErrorStr,
> - JITMemoryManager *JMM, unsigned
> OptLevel) {
> + JITMemoryManager *JMM,
> + CodeGenOpt::Level OptLevel) {
> const TargetMachineRegistry::entry *TheArch = MArch;
> if (TheArch == 0) {
> std::string Error;
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,7 @@
> #ifndef TARGET_ARM_H
> #define TARGET_ARM_H
>
> +#include "llvm/Target/TargetMachine.h"
> #include <cassert>
>
> namespace llvm {
> @@ -91,7 +92,8 @@
> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
> ARMTargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level OptLevel,
> + bool Verbose);
> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
> MachineCodeEmitter &MCE);
> FunctionPass *createARMLoadStoreOptimizationPass();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -138,17 +138,20 @@
>
>
> // Pass Pipeline Configuration
> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
> unsigned OptLevel) {
> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> PM.add(createARMISelDag(*this));
> return false;
> }
>
> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel) {
> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // FIXME: temporarily disabling load / store optimization pass for
> Thumb mode.
> - if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
> + if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !
> Subtarget.isThumb())
> PM.add(createARMLoadStoreOptimizationPass());
>
> - if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
> + if (OptLevel != CodeGenOpt::None &&
> + !DisableIfConversion && !Subtarget.isThumb())
> PM.add(createIfConverterPass());
>
> PM.add(createARMConstantIslandPass());
> @@ -156,7 +159,7 @@
> }
>
> bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> // Output assembly language.
> @@ -168,8 +171,10 @@
> }
>
>
> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> - bool DumpAsm,
> MachineCodeEmitter &MCE) {
> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> + bool DumpAsm,
> + MachineCodeEmitter &MCE) {
> // FIXME: Move this to TargetJITInfo!
> if (DefRelocModel == Reloc::Default)
> setRelocationModel(Reloc::Static);
> @@ -186,7 +191,7 @@
> }
>
> bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool DumpAsm,
> MachineCodeEmitter &MCE) {
> // Machine code emitter pass for ARM.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Apr 29 18:29:43
> 2009
> @@ -41,7 +41,8 @@
> // set this functions to ctor pointer at startup time if they are
> linked in.
> typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
> ARMTargetMachine &tm,
> - unsigned OptLevel, bool
> verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose);
> static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -69,14 +70,17 @@
> virtual const TargetAsmInfo *createTargetAsmInfo() const;
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> + virtual bool addCodeEmitter(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter &MCE);
> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> - bool DumpAsm,
> MachineCodeEmitter &MCE);
> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> + bool DumpAsm,
> + MachineCodeEmitter &MCE);
> };
>
> /// ThumbTargetMachine - Thumb target machine.
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Apr
> 29 18:29:43 2009
> @@ -81,7 +81,8 @@
> bool InCPMode;
> public:
> explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP
> (NULL),
> InCPMode(false) {
> Subtarget = &TM.getSubtarget<ARMSubtarget>();
> @@ -1061,7 +1062,8 @@
> ///
> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
> ARMTargetMachine &tm,
> - unsigned OptLevel,
> bool verbose) {
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose) {
> return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
>
> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Wed Apr 29 18:29:43 2009
> @@ -15,18 +15,20 @@
> #ifndef TARGET_ALPHA_H
> #define TARGET_ALPHA_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>
> class AlphaTargetMachine;
> class FunctionPass;
> - class TargetMachine;
> class MachineCodeEmitter;
> class raw_ostream;
>
> FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
> FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
> TargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool Verbose);
> FunctionPass *createAlphaPatternInstructionSelector(TargetMachine
> &TM);
> FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
> MachineCodeEmitter &MCE);
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -77,25 +77,26 @@
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> PM.add(createAlphaISelDag(*this));
> return false;
> }
> bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level OptLevel) {
> // Must run branch selection immediately preceding the asm printer
> PM.add(createAlphaBranchSelectionPass());
> return false;
> }
> bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> PM.add(createAlphaLLRPPass(*this));
> PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
> return false;
> }
> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
> unsigned OptLevel,
> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool DumpAsm,
> MachineCodeEmitter &MCE) {
> PM.add(createAlphaCodeEmitterPass(*this, MCE));
> if (DumpAsm)
> @@ -103,7 +104,8 @@
> return false;
> }
> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> bool DumpAsm,
> + CodeGenOpt::Level
> OptLevel,
> + bool DumpAsm,
> MachineCodeEmitter
> &MCE) {
> return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
> }
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -58,14 +58,17 @@
> static unsigned getModuleMatchQuality(const Module &M);
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> + virtual bool addCodeEmitter(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter &MCE);
> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> - bool DumpAsm,
> MachineCodeEmitter &MCE);
> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> + bool DumpAsm,
> + MachineCodeEmitter &MCE);
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed
> Apr 29 18:29:43 2009
> @@ -37,7 +37,8 @@
> ///
>
> explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(o, tm, T, OL, V) {}
>
> virtual const char *getPassName() const {
> @@ -68,7 +69,7 @@
> ///
> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
> TargetMachine &tm,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool verbose) {
> return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Apr 29 18:29:43
> 2009
> @@ -3587,7 +3587,7 @@
> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
> raw_ostream &o,
> CodeGenFileType
> FileType,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> if (FileType != TargetMachine::AssemblyFile) return true;
>
> PM.add(createGCLoweringPass());
>
> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -28,7 +28,7 @@
> virtual bool WantsWholeFile() const { return true; }
> virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
> &Out,
> CodeGenFileType FileType,
> - unsigned OptLevel);
> + CodeGenOpt::Level OptLevel);
>
> // This class always works, but must be requested explicitly on
> // llc command line.
>
> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed
> Apr 29 18:29:43 2009
> @@ -49,7 +49,8 @@
> std::set<std::string> FnStubs, GVStubs;
> public:
> explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V) :
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V) :
> AsmPrinter(O, TM, T, OL, V) {}
>
> virtual const char *getPassName() const {
> @@ -288,8 +289,9 @@
> DwarfWriter *DW;
> MachineModuleInfo *MMI;
> public:
> - LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
> - const TargetAsmInfo *T, bool F, bool V)
> + explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
> + const TargetAsmInfo *T,
> CodeGenOpt::Level F,
> + bool V)
> : SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>
> virtual const char *getPassName() const {
> @@ -615,6 +617,7 @@
> ///
> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
> SPUTargetMachine &tm,
> - unsigned OptLevel, bool
> verbose) {
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose) {
> return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Wed Apr 29 18:29:43 2009
> @@ -16,6 +16,7 @@
> #define LLVM_TARGET_IBMCELLSPU_H
>
> #include "llvm/Support/DataTypes.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
> class SPUTargetMachine;
> @@ -25,7 +26,8 @@
> FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
> FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
> SPUTargetMachine &tm,
> - unsigned OptLevel, bool
> verbose);
> + CodeGenOpt::Level OptLevel,
> + bool verbose);
>
> /*--== Utility functions/predicates/etc used all over the place: --
> ==*/
> //! Predicate test for a signed 10-bit value
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -81,7 +81,8 @@
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> bool
> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned
> OptLevel)
> +SPUTargetMachine::addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel)
> {
> // Install an instruction selector.
> PM.add(createSPUISelDag(*this));
> @@ -89,7 +90,7 @@
> }
>
> bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -83,8 +83,10 @@
> }
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Apr 29
> 18:29:43 2009
> @@ -1995,7 +1995,7 @@
> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
> raw_ostream &o,
> CodeGenFileType
> FileType,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> if (FileType != TargetMachine::AssemblyFile) return true;
> PM.add(new CppWriter(o));
> return false;
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -30,7 +30,7 @@
> virtual bool WantsWholeFile() const { return true; }
> virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
> &Out,
> CodeGenFileType FileType,
> - unsigned OptLevel);
> + CodeGenOpt::Level OptLevel);
>
> // This class always works, but shouldn't be the default in most
> cases.
> static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>
> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Wed Apr
> 29 18:29:43 2009
> @@ -25,7 +25,6 @@
> #include "llvm/CodeGen/DwarfWriter.h"
> #include "llvm/CodeGen/MachineFunctionPass.h"
> #include "llvm/Target/TargetAsmInfo.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Support/Mangler.h"
> #include "llvm/Support/raw_ostream.h"
> #include "llvm/ADT/Statistic.h"
> @@ -38,7 +37,8 @@
> std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
> public:
> explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V) {}
>
> virtual const char *getPassName() const {
> @@ -370,7 +370,7 @@
> ///
> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
> IA64TargetMachine &tm,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool verbose) {
> return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/IA64/IA64.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64.h Wed Apr 29 18:29:43 2009
> @@ -14,6 +14,8 @@
> #ifndef TARGET_IA64_H
> #define TARGET_IA64_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>
> class IA64TargetMachine;
> @@ -37,7 +39,8 @@
> ///
> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
> IA64TargetMachine &tm,
> - unsigned OptLevel, bool
> verbose);
> + CodeGenOpt::Level OptLevel,
> + bool verbose);
>
> } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -72,18 +72,20 @@
> // Pass Pipeline Configuration
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
> unsigned OptLEvel){
> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel){
> PM.add(createIA64DAGToDAGInstructionSelector(*this));
> return false;
> }
>
> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
> unsigned OptLevel) {
> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // Make sure everything is bundled happily
> PM.add(createIA64BundlingPass(*this));
> return true;
> }
> bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -51,9 +51,10 @@
> static unsigned getModuleMatchQuality(const Module &M);
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> };
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Wed Apr 29 18:29:43 2009
> @@ -36,7 +36,7 @@
> virtual bool WantsWholeFile() const { return true; }
> virtual bool addPassesToEmitWholeFile(PassManager &PM,
> raw_ostream &Out,
> CodeGenFileType FileType,
> - unsigned OptLevel);
> + CodeGenOpt::Level
> OptLevel);
>
> // This class always works, but shouldn't be the default in most
> cases.
> static unsigned getModuleMatchQuality(const Module &M) { return
> 1; }
> @@ -1664,7 +1664,7 @@
>
> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,
> raw_ostream &o,
> CodeGenFileType FileType,
> - unsigned OptLevel)
> + CodeGenOpt::Level OptLevel)
> {
> if (FileType != TargetMachine::AssemblyFile) return true;
> MSILWriter* Writer = new MSILWriter(o);
>
> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Wed Apr
> 29 18:29:43 2009
> @@ -50,7 +50,8 @@
> const MipsSubtarget *Subtarget;
> public:
> explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V) {
> Subtarget = &TM.getSubtarget<MipsSubtarget>();
> }
> @@ -91,7 +92,8 @@
> /// regardless of whether the function is in SSA form.
> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
> MipsTargetMachine &tm,
> - unsigned OptLevel,
> bool verbose) {
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose) {
> return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,8 @@
> #ifndef TARGET_MIPS_H
> #define TARGET_MIPS_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
> class MipsTargetMachine;
> class FunctionPass;
> @@ -25,7 +27,8 @@
> FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
> FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
> MipsTargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level OptLevel,
> + bool Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for Mips registers. This defines a
> mapping from
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -105,7 +105,7 @@
> // Install an instruction selector pass using
> // the ISelDag to gen Mips code.
> bool MipsTargetMachine::
> -addInstSelector(PassManagerBase &PM, unsigned OptLevel)
> +addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
> {
> PM.add(createMipsISelDag(*this));
> return false;
> @@ -115,7 +115,7 @@
> // machine code is emitted. return true if -print-machineinstrs should
> // print out the code after the passes.
> bool MipsTargetMachine::
> -addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
> +addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
> {
> PM.add(createMipsDelaySlotFillerPass(*this));
> return true;
> @@ -124,7 +124,7 @@
> // Implements the AssemblyEmitter for the target. Must return
> // true if AssemblyEmitter is supported
> bool MipsTargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
> +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out)
> {
> // Output assembly language.
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -57,9 +57,12 @@
> static unsigned getModuleMatchQuality(const Module &M);
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,7 @@
> #ifndef LLVM_TARGET_PIC16_H
> #define LLVM_TARGET_PIC16_H
>
> +#include "llvm/Target/TargetMachine.h"
> #include <iosfwd>
> #include <cassert>
>
> @@ -75,7 +76,8 @@
> FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
> FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
> PIC16TargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for PIC16 registers. This defines a
> mapping from
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Apr 29
> 18:29:43 2009
> @@ -161,7 +161,7 @@
> ///
> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
> PIC16TargetMachine &tm,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool verbose) {
> return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Wed Apr 29
> 18:29:43 2009
> @@ -25,7 +25,8 @@
> namespace llvm {
> struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
> explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V) {
> CurBank = "";
> FunctionLabelBegin = '@';
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -56,15 +56,15 @@
> }
>
> bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> // Install an instruction selector.
> PM.add(createPIC16ISelDag(*this));
> return false;
> }
>
> bool PIC16TargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool
> Verbose,
> - raw_ostream &Out) {
> +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
> + bool Verbose, raw_ostream &Out) {
> // Output assembly language.
> PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
> return false;
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -57,8 +57,10 @@
> return const_cast<PIC16TargetLowering*>(&TLInfo);
> }
>
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> }; // PIC16TargetMachine.
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed
> Apr 29 18:29:43 2009
> @@ -55,7 +55,8 @@
> const PPCSubtarget &Subtarget;
> public:
> explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V),
> Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>
> @@ -298,7 +299,8 @@
> MachineModuleInfo *MMI;
> public:
> explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> - const TargetAsmInfo *T, unsigned
> OL, bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>
> virtual const char *getPassName() const {
> @@ -327,7 +329,8 @@
> raw_ostream &OS;
> public:
> explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> - const TargetAsmInfo *T, unsigned
> OL, bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>
> virtual const char *getPassName() const {
> @@ -1176,7 +1179,8 @@
> ///
> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
> PPCTargetMachine &tm,
> - unsigned OptLevel, bool
> verbose) {
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose) {
> const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>
> if (Subtarget->isDarwin()) {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Wed Apr 29 18:29:43 2009
> @@ -18,6 +18,8 @@
> // GCC #defines PPC on Linux but we use it as our namespace name
> #undef PPC
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
> class PPCTargetMachine;
> class FunctionPass;
> @@ -28,7 +30,7 @@
> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
> PPCTargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level OptLevel,
> bool Verbose);
> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
> MachineCodeEmitter &MCE);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -129,21 +129,22 @@
> // Pass Pipeline Configuration
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
> unsigned OptLevel) {
> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // Install an instruction selector.
> PM.add(createPPCISelDag(*this));
> return false;
> }
>
> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel) {
> -
> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // Must run branch selection immediately preceding the asm printer.
> PM.add(createPPCBranchSelectionPass());
> return false;
> }
>
> bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
> @@ -153,7 +154,8 @@
> return false;
> }
>
> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool DumpAsm,
> MachineCodeEmitter &MCE) {
> // The JIT should use the static relocation model in ppc32 mode,
> PIC in ppc64.
> // FIXME: This should be moved to TargetJITInfo!!
> @@ -184,7 +186,8 @@
> return false;
> }
>
> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> unsigned OptLevel,
> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level
> OptLevel,
> bool DumpAsm,
> MachineCodeEmitter &MCE) {
> // Machine code emitter pass for PowerPC.
> PM.add(createPPCCodeEmitterPass(*this, MCE));
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -46,7 +46,8 @@
> // set this functions to ctor pointer at startup time if they are
> linked in.
> typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
> PPCTargetMachine &tm,
> - unsigned OptLevel, bool
> verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose);
> static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -76,13 +77,15 @@
> }
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> + virtual bool addCodeEmitter(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter &MCE);
> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter
> &MCE);
> virtual bool getEnableTailMergeDefault() const;
> };
>
> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Wed
> Apr 29 18:29:43 2009
> @@ -49,7 +49,8 @@
> ValueMapTy NumberForBB;
> public:
> explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V) {}
>
> virtual const char *getPassName() const {
> @@ -82,7 +83,7 @@
> ///
> FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
> TargetMachine &tm,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool verbose) {
> return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
> +++ llvm/trunk/lib/Target/Sparc/Sparc.h Wed Apr 29 18:29:43 2009
> @@ -15,17 +15,18 @@
> #ifndef TARGET_SPARC_H
> #define TARGET_SPARC_H
>
> +#include "llvm/Target/TargetMachine.h"
> #include <cassert>
>
> namespace llvm {
> class FunctionPass;
> - class TargetMachine;
> class SparcTargetMachine;
> class raw_ostream;
>
> FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
> FunctionPass *createSparcCodePrinterPass(raw_ostream &OS,
> TargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool Verbose);
> FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
> FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -69,7 +69,7 @@
> }
>
> bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> PM.add(createSparcISelDag(*this));
> return false;
> }
> @@ -77,14 +77,15 @@
> /// addPreEmitPass - This pass may be implemented by targets that
> want to run
> /// passes immediately before machine code is emitted. This should
> return
> /// true if -print-machineinstrs should print out the code after the
> passes.
> -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
> unsigned OptLevel){
> +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel){
> PM.add(createSparcFPMoverPass(*this));
> PM.add(createSparcDelaySlotFillerPass(*this));
> return true;
> }
>
> bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> // Output assembly language.
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -51,9 +51,10 @@
> static unsigned getModuleMatchQuality(const Module &M);
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreEmitPass(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Apr
> 29 18:29:43 2009
> @@ -34,7 +34,8 @@
> const X86Subtarget *Subtarget;
> public:
> explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
> Subtarget = &TM.getSubtarget<X86Subtarget>();
> }
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Wed Apr
> 29 18:29:43 2009
> @@ -25,7 +25,8 @@
> ///
> FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
> X86TargetMachine &tm,
> - unsigned OptLevel,
> bool verbose) {
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose) {
> const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
>
> if (Subtarget->isFlavorIntel()) {
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Wed
> Apr 29 18:29:43 2009
> @@ -26,7 +26,8 @@
>
> struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
> explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL,
> bool V)
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V) {}
>
> virtual const char *getPassName() const {
>
> Modified: llvm/trunk/lib/Target/X86/X86.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86.h (original)
> +++ llvm/trunk/lib/Target/X86/X86.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,8 @@
> #ifndef TARGET_X86_H
> #define TARGET_X86_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>
> class X86TargetMachine;
> @@ -25,7 +27,7 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned
> OptSize);
> +FunctionPass *createX86ISelDag(X86TargetMachine &TM,
> CodeGenOpt::Level OptLevel);
>
> /// createX86FloatingPointStackifierPass - This function returns a
> pass which
> /// converts floating point register references and pseudo
> instructions into
> @@ -44,7 +46,8 @@
> ///
> FunctionPass *createX86CodePrinterPass(raw_ostream &o,
> X86TargetMachine &tm,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level OptLevel,
> + bool Verbose);
>
> /// createX86CodeEmitterPass - Return a pass that emits the
> collected X86 code
> /// to the specified MCE object.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr 29
> 18:29:43 2009
> @@ -134,7 +134,7 @@
> bool OptForSize;
>
> public:
> - explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
> + explicit X86DAGToDAGISel(X86TargetMachine &tm,
> CodeGenOpt::Level OptLevel)
> : SelectionDAGISel(tm, OptLevel),
> TM(tm), X86Lowering(*TM.getTargetLowering()),
> Subtarget(&TM.getSubtarget<X86Subtarget>()),
> @@ -306,7 +306,7 @@
>
> bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
> SDNode *Root) const {
> - if (OptLevel == 0) return false;
> + if (OptLevel == CodeGenOpt::None) return false;
>
> if (U == Root)
> switch (U->getOpcode()) {
> @@ -714,7 +714,7 @@
> OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
>
> DEBUG(BB->dump());
> - if (OptLevel != 0)
> + if (OptLevel != CodeGenOpt::None)
> PreprocessForRMW();
>
> // FIXME: This should only happen when not compiled with -O0.
> @@ -1744,6 +1744,7 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned
> OptLevel) {
> +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
> + llvm::CodeGenOpt::Level
> OptLevel) {
> return new X86DAGToDAGISel(TM, OptLevel);
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -180,7 +180,8 @@
> // Pass Pipeline Configuration
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> -bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
> unsigned OptLevel) {
> +bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // Install an instruction selector.
> PM.add(createX86ISelDag(*this, OptLevel));
>
> @@ -194,20 +195,22 @@
> return false;
> }
>
> -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned
> OptLevel) {
> +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> // Calculate and set max stack object alignment early, so we can
> decide
> // whether we will need stack realignment (and thus FP).
> PM.add(createX86MaxStackAlignmentCalculatorPass());
> return false; // -print-machineinstr shouldn't print after this.
> }
>
> -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
> unsigned OptLevel) {
> +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel) {
> PM.add(createX86FloatingPointStackifierPass());
> return true; // -print-machineinstr should print after this.
> }
>
> bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
> @@ -216,7 +219,8 @@
> return false;
> }
>
> -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool DumpAsm,
> MachineCodeEmitter &MCE) {
> // FIXME: Move this to TargetJITInfo!
> // On Darwin, do not override 64-bit setting made in
> X86TargetMachine().
> @@ -245,7 +249,8 @@
> }
>
> bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> - unsigned OptLevel, bool
> DumpAsm,
> + CodeGenOpt::Level
> OptLevel,
> + bool DumpAsm,
> MachineCodeEmitter &MCE) {
> PM.add(createX86CodeEmitterPass(*this, MCE));
> if (DumpAsm) {
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Wed Apr 29 18:29:43
> 2009
> @@ -45,7 +45,8 @@
> // set this functions to ctor pointer at startup time if they are
> linked in.
> typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
> X86TargetMachine &tm,
> - unsigned OptLevel, bool
> verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool verbose);
> static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -74,14 +75,16 @@
> }
>
> // Set up the pass pipeline.
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPreRegAlloc(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addPostRegAlloc(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> - virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> + virtual bool addCodeEmitter(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter &MCE);
> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool DumpAsm, MachineCodeEmitter
> &MCE);
>
> /// symbolicAddressesAreRIPRel - Return true if symbolic addresses
> are
>
> Modified: llvm/trunk/lib/Target/XCore/XCore.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCore.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCore.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,8 @@
> #ifndef TARGET_XCORE_H
> #define TARGET_XCORE_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
> class FunctionPass;
> class TargetMachine;
> @@ -24,7 +26,8 @@
> FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
> FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
> XCoreTargetMachine &TM,
> - unsigned OptLevel, bool
> Verbose);
> + CodeGenOpt::Level
> OptLevel,
> + bool Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for XCore registers. This defines a
> mapping from
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Apr 29
> 18:29:43 2009
> @@ -57,8 +57,9 @@
> DwarfWriter *DW;
> const XCoreSubtarget &Subtarget;
> public:
> - XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
> - const TargetAsmInfo *T, unsigned OL, bool V)
> + explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
> + const TargetAsmInfo *T,
> CodeGenOpt::Level OL,
> + bool V)
> : AsmPrinter(O, TM, T, OL, V), DW(0),
> Subtarget(*TM.getSubtargetImpl()) {}
>
> @@ -105,7 +106,7 @@
> ///
> FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
> XCoreTargetMachine &tm,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool verbose) {
> return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Apr 29
> 18:29:43 2009
> @@ -56,13 +56,13 @@
> }
>
> bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
> - unsigned OptLevel) {
> + CodeGenOpt::Level
> OptLevel) {
> PM.add(createXCoreISelDag(*this));
> return false;
> }
>
> bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> - unsigned OptLevel,
> + CodeGenOpt::Level
> OptLevel,
> bool Verbose,
> raw_ostream &Out) {
> // Output assembly language.
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Wed Apr 29
> 18:29:43 2009
> @@ -52,8 +52,9 @@
> static unsigned getModuleMatchQuality(const Module &M);
>
> // Pass Pipeline Configuration
> - virtual bool addInstSelector(PassManagerBase &PM, unsigned
> OptLevel);
> - virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
> OptLevel,
> + virtual bool addInstSelector(PassManagerBase &PM,
> CodeGenOpt::Level OptLevel);
> + virtual bool addAssemblyEmitter(PassManagerBase &PM,
> + CodeGenOpt::Level OptLevel,
> bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/tools/llc/llc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/tools/llc/llc.cpp (original)
> +++ llvm/trunk/tools/llc/llc.cpp Wed Apr 29 18:29:43 2009
> @@ -56,12 +56,12 @@
> static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
>
> // Determine optimization level. Level -O0 is equivalent to "fast"
> code gen.
> -static cl::opt<unsigned>
> +static cl::opt<char>
> OptLevel("O",
> - cl::desc("Optimization level. Similar to llvm-gcc -O.
> (default: -O3)"),
> + cl::desc("Optimization level. Similar to llvm-gcc -O."),
> cl::Prefix,
> cl::ZeroOrMore,
> - cl::init(3));
> + cl::init(' '));
>
> static cl::opt<std::string>
> TargetTriple("mtriple", cl::desc("Override target triple for
> module"));
> @@ -253,6 +253,19 @@
> raw_ostream *Out = GetOutputStream(argv[0]);
> if (Out == 0) return 1;
>
> + CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive;
> +
> + switch (OptLevel) {
> + default:
> + case ' ': break;
> + case '0': OLvl = CodeGenOpt::None; break;
> + case '1': OLvl = CodeGenOpt::One; break;
> + case '2': OLvl = CodeGenOpt::Two; break;
> + case 's': OLvl = CodeGenOpt::Size; break;
> + case '3': OLvl = CodeGenOpt::Aggressive; break;
> + case '4': OLvl = CodeGenOpt::LTO; break;
> + }
> +
> // If this target requires addPassesToEmitWholeFile, do it now.
> This is
> // used by strange things like the C backend.
> if (Target.WantsWholeFile()) {
> @@ -262,7 +275,7 @@
> PM.add(createVerifierPass());
>
> // Ask the target to add backend passes as necessary.
> - if (Target.addPassesToEmitWholeFile(PM, *Out, FileType,
> OptLevel)) {
> + if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) {
> std::cerr << argv[0] << ": target does not support generation
> of this"
> << " file type!\n";
> if (Out != &outs()) delete Out;
> @@ -288,7 +301,7 @@
> // Override default to generate verbose assembly.
> Target.setAsmVerbosityDefault(true);
>
> - switch (Target.addPassesToEmitFile(Passes, *Out, FileType,
> OptLevel)) {
> + switch (Target.addPassesToEmitFile(Passes, *Out, FileType,
> OLvl)) {
> default:
> assert(0 && "Invalid file model!");
> return 1;
> @@ -309,7 +322,7 @@
> break;
> }
>
> - if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
> + if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) {
> std::cerr << argv[0] << ": target does not support generation
> of this"
> << " file type!\n";
> if (Out != &outs()) delete Out;
>
> Modified: llvm/trunk/tools/lli/lli.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/tools/lli/lli.cpp (original)
> +++ llvm/trunk/tools/lli/lli.cpp Wed Apr 29 18:29:43 2009
> @@ -122,7 +122,9 @@
> if (!TargetTriple.empty())
> Mod->setTargetTriple(TargetTriple);
>
> - EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
> Fast);
> + EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
> + Fast ?
> + CodeGenOpt::None :
> CodeGenOpt::Aggressive);
> if (!EE && !ErrorMsg.empty()) {
> std::cerr << argv[0] << ":error creating EE: " << ErrorMsg <<
> "\n";
> exit(1);
>
> Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
> +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Apr 29 18:29:43 2009
> @@ -442,7 +442,8 @@
> MachineCodeEmitter* mce = NULL;
>
> switch (_target->addPassesToEmitFile(*codeGenPasses, out,
> - TargetMachine::AssemblyFile,
> 3)) {
> + TargetMachine::AssemblyFile,
> + CodeGenOpt::Default)) {
> case FileModel::MachOFile:
> mce = AddMachOWriter(*codeGenPasses, out, *_target);
> break;
> @@ -457,7 +458,8 @@
> return true;
> }
>
> - if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
> + if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
> + CodeGenOpt::Default)) {
> errMsg = "target does not support generation of this file
> type";
> return true;
> }
>
> Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Wed Apr 29
> 18:29:43 2009
> @@ -650,7 +650,7 @@
> O << "\";\n\n";
>
> O << " if (TAI->doesSupportDebugInformation() &&\n"
> - << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
> + << " DW->ShouldEmitDwarfDebug() && OptLevel !=
> CodeGenOpt::None) {\n"
> << " DebugLoc CurDL = MI->getDebugLoc();\n\n"
> << " if (!CurDL.isUnknown()) {\n"
> << " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Apr 29 18:29:43
> 2009
> @@ -465,7 +465,7 @@
> NumInputRootOps = N->getNumChildren();
>
> if (DisablePatternForFastISel(N, CGP))
> - emitCheck("OptLevel != 0");
> + emitCheck("OptLevel != CodeGenOpt::None");
>
> emitCheck(PredicateCheck);
> }
>
>
> _______________________________________________
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