[llvm-commits] [llvm] r70270 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib
Bill Wendling
isanbard at gmail.com
Mon Apr 27 17:34:01 PDT 2009
There weren't any llvmgcc changes that I could see. I.e., I couldn't
see where it was passing -fast...
-bw
On Mon, Apr 27, 2009 at 5:32 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Also llvmgcc changes?
>
> Evan
>
> On Apr 27, 2009, at 5:30 PM, Evan Cheng wrote:
>
>> Thanks. How about libLTO?
>>
>> Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has to
>> be changed as well.
>>
>> Evan
>>
>> On Apr 27, 2009, at 5:21 PM, Bill Wendling wrote:
>>
>>> Author: void
>>> Date: Mon Apr 27 19:21:31 2009
>>> New Revision: 70270
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
>>> Log:
>>> Massive check in. This changes the "-fast" flag to "-O#" in llc. If
>>> you want to
>>> use the old behavior, the flag is -O0. This change allows for finer-
>>> grained
>>> control over which optimizations are run at different -O levels.
>>>
>>> Most of this work was pretty mechanical. The majority of the fixes
>>> came from
>>> verifying that a "fast" variable wasn't used anymore. The JIT still
>>> uses a
>>> "Fast" flag. I'm not 100% sure if it's necessary to change it
>>> there...
>>>
>>> Modified:
>>> llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>> llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>> llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>> llvm/trunk/include/llvm/Target/TargetMachine.h
>>> llvm/trunk/include/llvm/Target/TargetOptions.h
>>> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>> llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> llvm/trunk/lib/Target/ARM/ARM.h
>>> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>> llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>> llvm/trunk/lib/Target/Alpha/Alpha.h
>>> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>> llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>> llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>> llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> llvm/trunk/lib/Target/CellSPU/SPU.h
>>> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>> llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>> llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>> llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> llvm/trunk/lib/Target/IA64/IA64.h
>>> llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>> llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>> llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>> llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> llvm/trunk/lib/Target/Mips/Mips.h
>>> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>> llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>> llvm/trunk/lib/Target/PIC16/PIC16.h
>>> llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>> llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>> llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>> llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>> llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> llvm/trunk/lib/Target/PowerPC/PPC.h
>>> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>> llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>> llvm/trunk/lib/Target/Sparc/Sparc.h
>>> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>>> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>>> llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>>> llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>>> llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>>> llvm/trunk/lib/Target/X86/X86.h
>>> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>> llvm/trunk/lib/Target/X86/X86TargetMachine.h
>>> llvm/trunk/lib/Target/XCore/XCore.h
>>> llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>>> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>>> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>>> llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>>> llvm/trunk/test/CodeGen/Generic/2006-06-13-
>>> ComputeMaskedBitsCrash.ll
>>> llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>>> llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>>> llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>>> llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>>> llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>>> llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>>> llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>>> llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>>> llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>>> llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>>> llvm/trunk/test/CodeGen/X86/pr1489.ll
>>> llvm/trunk/test/CodeGen/X86/volatile.ll
>>> llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>>> llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>>> llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>>> llvm/trunk/test/DebugInfo/forwardDecl.ll
>>> llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>>> llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>>> llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>>> llvm/trunk/tools/llc/llc.cpp
>>> llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>>> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 19:21:31
>>> 2009
>>> @@ -65,8 +65,8 @@
>>> // Necessary for external weak linkage support
>>> std::set<const GlobalValue*> ExtWeakSymbols;
>>>
>>> - /// Fast - Generating code via fast instruction selection.
>>> - bool Fast;
>>> + /// OptLevel - Generating code at a specific optimization level.
>>> + unsigned OptLevel;
>>> public:
>>> /// Output stream on which we're printing assembly code.
>>> ///
>>> @@ -110,8 +110,8 @@
>>> bool VerboseAsm;
>>>
>>> protected:
>>> - AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V);
>>> + explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL, bool
>>> V);
>>>
>>> public:
>>> virtual ~AsmPrinter();
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -81,7 +81,7 @@
>>> void EndFunction(MachineFunction *MF);
>>>
>>> /// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> - bool ValidDebugInfo(Value *V, bool FastISel);
>>> + bool ValidDebugInfo(Value *V, unsigned OptLevel);
>>>
>>> /// RecordSourceLine - Register a source line with debug info.
>>> Returns a
>>> /// unique label ID used to generate a label and provide
>>> correspondence to
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon
>>> Apr 27 19:21:31 2009
>>> @@ -42,11 +42,11 @@
>>> llvm::linkOcamlGC();
>>> llvm::linkShadowStackGC();
>>>
>>> - (void) llvm::createBURRListDAGScheduler(NULL, false);
>>> - (void) llvm::createTDRRListDAGScheduler(NULL, false);
>>> - (void) llvm::createTDListDAGScheduler(NULL, false);
>>> - (void) llvm::createFastDAGScheduler(NULL, false);
>>> - (void) llvm::createDefaultScheduler(NULL, false);
>>> + (void) llvm::createBURRListDAGScheduler(NULL, 3);
>>> + (void) llvm::createTDRRListDAGScheduler(NULL, 3);
>>> + (void) llvm::createTDListDAGScheduler(NULL, 3);
>>> + (void) llvm::createFastDAGScheduler(NULL, 3);
>>> + (void) llvm::createDefaultScheduler(NULL, 3);
>>>
>>> }
>>> } ForceCodegenLinking; // Force link by creating a global
>>> definition.
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -32,7 +32,7 @@
>>>
>>> class RegisterScheduler : public MachinePassRegistryNode {
>>> public:
>>> - typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>> (SelectionDAGISel*, bool);
>>> + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>> (SelectionDAGISel*, unsigned);
>>>
>>> static MachinePassRegistry Registry;
>>>
>>> @@ -64,27 +64,27 @@
>>> /// createBURRListDAGScheduler - This creates a bottom up register
>>> usage
>>> /// reduction list scheduler.
>>> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> /// createTDRRListDAGScheduler - This creates a top down register
>>> usage
>>> /// reduction list scheduler.
>>> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> /// createTDListDAGScheduler - This creates a top-down list
>>> scheduler with
>>> /// a hazard recognizer.
>>> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> /// createFastDAGScheduler - This creates a "fast" scheduler.
>>> ///
>>> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> /// createDefaultScheduler - This creates an instruction scheduler
>>> appropriate
>>> /// for the target.
>>> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> } // end namespace llvm
>>>
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -202,7 +202,7 @@
>>> /// certain types of nodes together, or eliminating superfluous
>>> nodes. The
>>> /// Level argument controls whether Combine is allowed to produce
>>> nodes and
>>> /// types that are illegal on the target.
>>> - void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
>>> + void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned
>>> OptLevel);
>>>
>>> /// LegalizeTypes - This transforms the SelectionDAG into a
>>> SelectionDAG that
>>> /// only uses types natively supported by the target. Returns
>>> "true" if it
>>> @@ -218,7 +218,7 @@
>>> ///
>>> /// Note that this is an involved process that may invalidate
>>> pointers into
>>> /// the graph.
>>> - void Legalize(bool TypesNeedLegalizing, bool Fast);
>>> + void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>>>
>>> /// RemoveDeadNodes - This method deletes all unreachable nodes in
>>> the
>>> /// SelectionDAG.
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -51,10 +51,10 @@
>>> MachineBasicBlock *BB;
>>> AliasAnalysis *AA;
>>> GCFunctionInfo *GFI;
>>> - bool Fast;
>>> + unsigned OptLevel;
>>> static char ID;
>>>
>>> - explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
>>> + explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>>> virtual ~SelectionDAGISel();
>>>
>>> TargetLowering &getTargetLowering() { return TLI; }
>>>
>>> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
>>> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -213,7 +213,7 @@
>>> virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>>> raw_ostream &,
>>> CodeGenFileType,
>>> - bool /*Fast*/) {
>>> + unsigned /* OptLevel
>>> */) {
>>> return FileModel::None;
>>> }
>>>
>>> @@ -222,7 +222,8 @@
>>> /// used to finish up adding passes to emit the file, if necessary.
>>> ///
>>> virtual bool addPassesToEmitFileFinish(PassManagerBase &,
>>> - MachineCodeEmitter *,
>>> bool /*Fast*/) {
>>> + MachineCodeEmitter *,
>>> + unsigned /* OptLevel */) {
>>> return true;
>>> }
>>>
>>> @@ -234,7 +235,7 @@
>>> ///
>>> virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>>> MachineCodeEmitter &,
>>> - bool /*Fast*/) {
>>> + unsigned /* OptLevel */) {
>>> return true;
>>> }
>>>
>>> @@ -243,7 +244,8 @@
>>> /// use this.
>>> virtual bool WantsWholeFile() const { return false; }
>>> virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
>>> - CodeGenFileType, bool /
>>> *Fast*/) {
>>> + CodeGenFileType,
>>> + unsigned /* OptLevel */) {
>>> return true;
>>> }
>>> };
>>> @@ -258,16 +260,16 @@
>>> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>> for
>>> /// both emitting to assembly files or machine code output.
>>> ///
>>> - bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
>>> + bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*
>>> OptLevel */);
>>>
>>> public:
>>>
>>> /// addPassesToEmitFile - Add passes to the specified pass manager
>>> to get the
>>> /// specified file emitted. Typically this will involve several
>>> steps of code
>>> - /// generation. If Fast is set to true, the code generator
>>> should emit code
>>> - /// as fast as possible, though the generated code may be less
>>> efficient.
>>> - /// This method should return FileModel::Error if emission of
>>> this file type
>>> - /// is not supported.
>>> + /// generation. If OptLevel is 0, the code generator should emit
>>> code as fast
>>> + /// as possible, though the generated code may be less
>>> efficient. This method
>>> + /// should return FileModel::Error if emission of this file type
>>> is not
>>> + /// supported.
>>> ///
>>> /// The default implementation of this method adds components from
>>> the
>>> /// LLVM retargetable code generator, invoking the methods below
>>> to get
>>> @@ -276,14 +278,15 @@
>>> virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>>> raw_ostream &Out,
>>> CodeGenFileType
>>> FileType,
>>> - bool Fast);
>>> + unsigned OptLevel);
>>>
>>> /// addPassesToEmitFileFinish - If the passes to emit the
>>> specified file had
>>> /// to be split up (e.g., to add an object writer pass), this
>>> method can be
>>> /// used to finish up adding passes to emit the file, if necessary.
>>> ///
>>> virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
>>> - MachineCodeEmitter *MCE,
>>> bool Fast);
>>> + MachineCodeEmitter *MCE,
>>> + unsigned OptLevel);
>>>
>>> /// addPassesToEmitMachineCode - Add passes to the specified pass
>>> manager to
>>> /// get machine code emitted. This uses a MachineCodeEmitter
>>> object to handle
>>> @@ -292,21 +295,22 @@
>>> /// not supported.
>>> ///
>>> virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
>>> - MachineCodeEmitter &MCE,
>>> bool Fast);
>>> + MachineCodeEmitter &MCE,
>>> + unsigned OptLevel);
>>>
>>> /// Target-Independent Code Generator Pass Configuration Options.
>>>
>>> /// addInstSelector - This method should add any "last minute"
>>> LLVM->LLVM
>>> /// passes, then install an instruction selector pass, which
>>> converts from
>>> /// LLVM code to machine instructions.
>>> - virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
>>> + virtual bool addInstSelector(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> return true;
>>> }
>>>
>>> /// addPreRegAllocPasses - This method may be implemented by
>>> targets that want
>>> /// to run passes immediately before register allocation. This
>>> should return
>>> /// true if -print-machineinstrs should print after these passes.
>>> - virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>> + virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> return false;
>>> }
>>>
>>> @@ -314,14 +318,14 @@
>>> /// want to run passes after register allocation but before prolog-
>>> epilog
>>> /// insertion. This should return true if -print-machineinstrs
>>> should print
>>> /// after these passes.
>>> - virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>> + virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> return false;
>>> }
>>>
>>> /// addPreEmitPass - This pass may be implemented by targets that
>>> want to run
>>> /// passes immediately before machine code is emitted. This
>>> should return
>>> /// true if -print-machineinstrs should print out the code after
>>> the passes.
>>> - virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
>>> + virtual bool addPreEmitPass(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> return false;
>>> }
>>>
>>> @@ -329,7 +333,7 @@
>>> /// addAssemblyEmitter - This pass should be overridden by the
>>> target to add
>>> /// the asmprinter, if asm emission is supported. If this is not
>>> supported,
>>> /// 'true' should be returned.
>>> - virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
>>> + virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> bool /* VerboseAsmDefault */,
>>> raw_ostream &) {
>>> return true;
>>> }
>>> @@ -337,7 +341,7 @@
>>> /// addCodeEmitter - This pass should be overridden by the target
>>> to add a
>>> /// code emitter, if supported. If this is not supported, 'true'
>>> should be
>>> /// returned. If DumpAsm is true, the generated assembly is
>>> printed to cerr.
>>> - virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
>>> + virtual bool addCodeEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> bool /*DumpAsm*/, MachineCodeEmitter
>>> &) {
>>> return true;
>>> }
>>> @@ -346,7 +350,7 @@
>>> /// a code emitter (without setting flags), if supported. If this
>>> is not
>>> /// supported, 'true' should be returned. If DumpAsm is true, the
>>> generated
>>> /// assembly is printed to cerr.
>>> - virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /
>>> *Fast*/,
>>> + virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> bool /*DumpAsm*/,
>>> MachineCodeEmitter &) {
>>> return true;
>>> }
>>>
>>> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
>>> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -108,7 +108,7 @@
>>> /// generated.
>>> extern bool DisableJumpTables;
>>>
>>> - /// FastISel - This flag enables fast-path instruction selection
>>> + /// EnableFastISel - This flag enables fast-path instruction
>>> selection
>>> /// which trades away generated code quality in favor of reducing
>>> /// compile time.
>>> extern bool EnableFastISel;
>>>
>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -42,8 +42,8 @@
>>>
>>> char AsmPrinter::ID = 0;
>>> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> - const TargetAsmInfo *T, bool F, bool VDef)
>>> - : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
>>> + const TargetAsmInfo *T, unsigned OL, bool
>>> VDef)
>>> + : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>>> TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>>> IsInTextSection(false)
>>> {
>>>
>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -3351,7 +3351,7 @@
>>> }
>>>
>>> /// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> - bool ValidDebugInfo(Value *V, bool FastISel) {
>>> + bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>>> if (!V)
>>> return false;
>>>
>>> @@ -3393,7 +3393,7 @@
>>> case DW_TAG_lexical_block:
>>> /// FIXME. This interfers with the qualitfy of generated code
>>> when
>>> /// during optimization.
>>> - if (FastISel == false)
>>> + if (OptLevel != 0)
>>> return false;
>>> default:
>>> break;
>>> @@ -4730,8 +4730,8 @@
>>> }
>>>
>>> /// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
>>> - return DD && DD->ValidDebugInfo(V, FastISel);
>>> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
>>> + return DD && DD->ValidDebugInfo(V, OptLevel);
>>> }
>>>
>>> /// RecordSourceLine - Records location information and associates
>>> it with a
>>>
>>> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -55,9 +55,9 @@
>>> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>>> raw_ostream &Out,
>>> CodeGenFileType FileType,
>>> - bool Fast) {
>>> + unsigned OptLevel) {
>>> // Add common CodeGen passes.
>>> - if (addCommonCodeGenPasses(PM, Fast))
>>> + if (addCommonCodeGenPasses(PM, OptLevel))
>>> return FileModel::Error;
>>>
>>> // Fold redundant debug labels.
>>> @@ -66,17 +66,17 @@
>>> if (PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>> + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - if (!Fast)
>>> + if (OptLevel != 0)
>>> PM.add(createLoopAlignerPass());
>>>
>>> switch (FileType) {
>>> default:
>>> break;
>>> case TargetMachine::AssemblyFile:
>>> - if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
>>> + if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),
>>> Out))
>>> return FileModel::Error;
>>> return FileModel::AsmFile;
>>> case TargetMachine::ObjectFile:
>>> @@ -94,9 +94,9 @@
>>> /// finish up adding passes to emit the file, if necessary.
>>> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase
>>> &PM,
>>> MachineCodeEmitter
>>> *MCE,
>>> - bool Fast) {
>>> + unsigned
>>> OptLevel) {
>>> if (MCE)
>>> - addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
>>> + addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>>>
>>> PM.add(createGCInfoDeleter());
>>>
>>> @@ -114,15 +114,15 @@
>>> ///
>>> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase
>>> &PM,
>>>
>>> MachineCodeEmitter &MCE,
>>> - bool Fast) {
>>> + unsigned
>>> OptLevel) {
>>> // Add common CodeGen passes.
>>> - if (addCommonCodeGenPasses(PM, Fast))
>>> + if (addCommonCodeGenPasses(PM, OptLevel))
>>> return true;
>>>
>>> - if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>> + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
>>> + addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>>>
>>> PM.add(createGCInfoDeleter());
>>>
>>> @@ -135,11 +135,12 @@
>>> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>> for
>>> /// both emitting to assembly files or machine code output.
>>> ///
>>> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>>> bool Fast) {
>>> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>>> + unsigned OptLevel) {
>>> // Standard LLVM-Level Passes.
>>>
>>> // Run loop strength reduction before anything else.
>>> - if (!Fast) {
>>> + if (OptLevel != 0) {
>>> PM.add(createLoopStrengthReducePass(getTargetLowering()));
>>> if (PrintLSR)
>>> PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",
>>> &errs()));
>>> @@ -153,7 +154,7 @@
>>> // Make sure that no unreachable blocks are instruction selected.
>>> PM.add(createUnreachableBlockEliminationPass());
>>>
>>> - if (!Fast)
>>> + if (OptLevel != 0)
>>> PM.add(createCodeGenPreparePass(getTargetLowering()));
>>>
>>> PM.add(createStackProtectorPass(getTargetLowering()));
>>> @@ -167,38 +168,38 @@
>>>
>>> // Enable FastISel with -fast, but allow that to be overridden.
>>> if (EnableFastISelOption == cl::BOU_TRUE ||
>>> - (Fast && EnableFastISelOption != cl::BOU_FALSE))
>>> + (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>>> EnableFastISel = true;
>>>
>>> // Ask the target for an isel.
>>> - if (addInstSelector(PM, Fast))
>>> + if (addInstSelector(PM, OptLevel))
>>> return true;
>>>
>>> // Print the instruction selected machine code...
>>> if (PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - if (!Fast) {
>>> + if (OptLevel != 0) {
>>> PM.add(createMachineLICMPass());
>>> PM.add(createMachineSinkingPass());
>>> }
>>>
>>> // Run pre-ra passes.
>>> - if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
>>> + if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> // Perform register allocation.
>>> PM.add(createRegisterAllocator());
>>>
>>> // Perform stack slot coloring.
>>> - if (!Fast)
>>> + if (OptLevel != 0)
>>> PM.add(createStackSlotColoringPass());
>>>
>>> if (PrintMachineCode) // Print the register-allocated code
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> // Run post-ra passes.
>>> - if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
>>> + if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> if (PrintMachineCode)
>>> @@ -216,7 +217,7 @@
>>> PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> // Second pass scheduler.
>>> - if (!Fast && !DisablePostRAScheduler) {
>>> + if (OptLevel != 0 && !DisablePostRAScheduler) {
>>> PM.add(createPostRAScheduler());
>>>
>>> if (PrintMachineCode)
>>> @@ -224,7 +225,7 @@
>>> }
>>>
>>> // Branch folding must be run after regalloc and prolog/epilog
>>> insertion.
>>> - if (!Fast)
>>> + if (OptLevel != 0)
>>> PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>>>
>>> if (PrintMachineCode)
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,9 +57,9 @@
>>> SelectionDAG &DAG;
>>> const TargetLowering &TLI;
>>> CombineLevel Level;
>>> + unsigned OptLevel;
>>> bool LegalOperations;
>>> bool LegalTypes;
>>> - bool Fast;
>>>
>>> // Worklist of all of the nodes that need to be simplified.
>>> std::vector<SDNode*> WorkList;
>>> @@ -254,13 +254,13 @@
>>> }
>>>
>>> public:
>>> - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
>>> + DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>>> : DAG(D),
>>> TLI(D.getTargetLoweringInfo()),
>>> Level(Unrestricted),
>>> + OptLevel(OL),
>>> LegalOperations(false),
>>> LegalTypes(false),
>>> - Fast(fast),
>>> AA(A) {}
>>>
>>> /// Run - runs the dag combiner on all nodes in the work list
>>> @@ -4784,7 +4784,7 @@
>>> SDValue Ptr = LD->getBasePtr();
>>>
>>> // Try to infer better alignment information than the load already
>>> has.
>>> - if (!Fast && LD->isUnindexed()) {
>>> + if (OptLevel != 0 && LD->isUnindexed()) {
>>> if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>> if (Align > LD->getAlignment())
>>> return DAG.getExtLoad(LD->getExtensionType(), N-
>>>> getDebugLoc(),
>>> @@ -4904,7 +4904,7 @@
>>> SDValue Ptr = ST->getBasePtr();
>>>
>>> // Try to infer better alignment information than the store
>>> already has.
>>> - if (!Fast && ST->isUnindexed()) {
>>> + if (OptLevel != 0 && ST->isUnindexed()) {
>>> if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>> if (Align > ST->getAlignment())
>>> return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
>>> @@ -6084,8 +6084,9 @@
>>>
>>> // SelectionDAG::Combine - This is the entry point for the file.
>>> //
>>> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>> bool Fast) {
>>> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>> + unsigned OptLevel) {
>>> /// run - This is the main entry point to this class.
>>> ///
>>> - DAGCombiner(*this, AA, Fast).Run(Level);
>>> + DAGCombiner(*this, AA, OptLevel).Run(Level);
>>> }
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -327,7 +327,7 @@
>>> default: break;
>>> case Intrinsic::dbg_stoppoint: {
>>> DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>>> - if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
>>> + if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>>> DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>>> std::string Dir, FN;
>>> unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
>>> @@ -344,7 +344,7 @@
>>> }
>>> case Intrinsic::dbg_region_start: {
>>> DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
>>> - if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
>>> + if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>>> unsigned ID =
>>> DW->RecordRegionStart(cast<GlobalVariable>(RSI-
>>>> getContext()));
>>> const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
>>> @@ -354,7 +354,7 @@
>>> }
>>> case Intrinsic::dbg_region_end: {
>>> DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
>>> - if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
>>> + if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>>> unsigned ID = 0;
>>> DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>>> if (!Subprogram.isNull() && !
>>> Subprogram.describes(MF.getFunction())) {
>>> @@ -380,7 +380,7 @@
>>> DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>>> Value *SP = FSI->getSubprogram();
>>>
>>> - if (DW->ValidDebugInfo(SP, true)) {
>>> + if (DW->ValidDebugInfo(SP, 0)) {
>>> // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>> which is what
>>> // (most?) gdb expects.
>>> DebugLoc PrevLoc = DL;
>>> @@ -425,7 +425,7 @@
>>> case Intrinsic::dbg_declare: {
>>> DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>>> Value *Variable = DI->getVariable();
>>> - if (DW && DW->ValidDebugInfo(Variable, true)) {
>>> + if (DW && DW->ValidDebugInfo(Variable, 0)) {
>>> // Determine the address of the declared object.
>>> Value *Address = DI->getAddress();
>>> if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -55,8 +55,8 @@
>>> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>>> TargetLowering &TLI;
>>> SelectionDAG &DAG;
>>> + unsigned OptLevel;
>>> bool TypesNeedLegalizing;
>>> - bool Fast;
>>>
>>> // Libcall insertion helpers.
>>>
>>> @@ -139,7 +139,7 @@
>>>
>>> public:
>>> explicit SelectionDAGLegalize(SelectionDAG &DAG, bool
>>> TypesNeedLegalizing,
>>> - bool fast);
>>> + unsigned ol);
>>>
>>> /// getTypeAction - Return how we should legalize values of this
>>> type, either
>>> /// it is already legal or we need to expand it into multiple
>>> registers of
>>> @@ -345,9 +345,9 @@
>>> }
>>>
>>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
>>> - bool types, bool fast)
>>> - : TLI(dag.getTargetLoweringInfo()), DAG(dag),
>>> TypesNeedLegalizing(types),
>>> - Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
>>> + bool types, unsigned ol)
>>> + : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
>>> + TypesNeedLegalizing(types),
>>> ValueTypeActions(TLI.getValueTypeActions()) {
>>> assert(MVT::LAST_VALUETYPE <= 32 &&
>>> "Too many value types for ValueTypeActions to hold!");
>>> }
>>> @@ -1271,7 +1271,7 @@
>>> unsigned Line = DSP->getLine();
>>> unsigned Col = DSP->getColumn();
>>>
>>> - if (Fast) {
>>> + if (OptLevel == 0) {
>>> // A bit self-referential to have DebugLoc on Debug_Loc
>>> nodes, but it
>>> // won't hurt anything.
>>> if (useDEBUG_LOC) {
>>> @@ -8566,9 +8566,9 @@
>>>
>>> // SelectionDAG::Legalize - This is the entry point for the file.
>>> //
>>> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
>>> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned
>>> OptLevel) {
>>> /// run - This is the main entry point to this class.
>>> ///
>>> - SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>> Fast).LegalizeDAG();
>>> + SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>> OptLevel).LegalizeDAG();
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -630,6 +630,6 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> return new ScheduleDAGFast(*IS->MF);
>>> }
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -261,7 +261,7 @@
>>> /// new hazard recognizer. This scheduler takes ownership of the
>>> hazard
>>> /// recognizer and deletes it when done.
>>> ScheduleDAGSDNodes *
>>> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
>>> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> return new ScheduleDAGList(*IS->MF,
>>> new LatencyPriorityQueue(),
>>> IS->CreateTargetHazardRecognizer());
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -1505,7 +1505,7 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> const TargetMachine &TM = IS->TM;
>>> const TargetInstrInfo *TII = TM.getInstrInfo();
>>> const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>> @@ -1519,7 +1519,7 @@
>>> }
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> const TargetMachine &TM = IS->TM;
>>> const TargetInstrInfo *TII = TM.getInstrInfo();
>>> const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -3910,9 +3910,9 @@
>>> case Intrinsic::dbg_stoppoint: {
>>> DwarfWriter *DW = DAG.getDwarfWriter();
>>> DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
>>> - if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
>>> + if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>>> MachineFunction &MF = DAG.getMachineFunction();
>>> - if (Fast)
>>> + if (OptLevel == 0)
>>> DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>>> SPI.getLine(),
>>> SPI.getColumn(),
>>> @@ -3930,7 +3930,8 @@
>>> case Intrinsic::dbg_region_start: {
>>> DwarfWriter *DW = DAG.getDwarfWriter();
>>> DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
>>> - if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
>>> +
>>> + if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>>> unsigned LabelID =
>>> DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>>> DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
>>> @@ -3942,8 +3943,8 @@
>>> case Intrinsic::dbg_region_end: {
>>> DwarfWriter *DW = DAG.getDwarfWriter();
>>> DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
>>> - if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>>>
>>> + if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>>> MachineFunction &MF = DAG.getMachineFunction();
>>> DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
>>> std::string SPName;
>>> @@ -3952,7 +3953,7 @@
>>> && strcmp(SPName.c_str(), MF.getFunction()-
>>>> getNameStart())) {
>>> // This is end of inlined function. Debugging information
>>> for
>>> // inlined function is not handled yet (only supported by
>>> FastISel).
>>> - if (Fast) {
>>> + if (OptLevel == 0) {
>>> unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>>> if (ID != 0)
>>> // Returned ID is 0 if this is unbalanced "end of inlined
>>> @@ -3978,9 +3979,9 @@
>>> if (!DW) return 0;
>>> DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>>> Value *SP = FSI.getSubprogram();
>>> - if (SP && DW->ValidDebugInfo(SP, Fast)) {
>>> - MachineFunction &MF = DAG.getMachineFunction();
>>> - if (Fast) {
>>> + if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
>>> + MachineFunction &MF = DAG.getMachineFunction();
>>> + if (OptLevel == 0) {
>>> // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>> which is what
>>> // (most?) gdb expects.
>>> DebugLoc PrevLoc = CurDebugLoc;
>>> @@ -4051,11 +4052,11 @@
>>> return 0;
>>> }
>>> case Intrinsic::dbg_declare: {
>>> - if (Fast) {
>>> + if (OptLevel == 0) {
>>> DwarfWriter *DW = DAG.getDwarfWriter();
>>> DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>>> Value *Variable = DI.getVariable();
>>> - if (DW && DW->ValidDebugInfo(Variable, Fast))
>>> + if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>>> DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other,
>>> getRoot(),
>>> getValue(DI.getAddress()),
>>> getValue(Variable)));
>>> } else {
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr
>>> 27 19:21:31 2009
>>> @@ -355,17 +355,17 @@
>>> ///
>>> FunctionLoweringInfo &FuncInfo;
>>>
>>> - /// Fast - We are in -fast mode.
>>> + /// OptLevel - What optimization level we're generating code for.
>>> ///
>>> - bool Fast;
>>> + unsigned OptLevel;
>>>
>>> /// GFI - Garbage collection metadata for the function.
>>> GCFunctionInfo *GFI;
>>>
>>> SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
>>> - FunctionLoweringInfo &funcinfo, bool fast)
>>> + FunctionLoweringInfo &funcinfo, unsigned ol)
>>> : CurDebugLoc(DebugLoc::getUnknownLoc()),
>>> - TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
>>> + TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>>> }
>>>
>>> void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -136,16 +136,16 @@
>>> /// createDefaultScheduler - This creates an instruction scheduler
>>> appropriate
>>> /// for the target.
>>> ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
>>> - bool Fast) {
>>> + unsigned OptLevel) {
>>> const TargetLowering &TLI = IS->getTargetLowering();
>>>
>>> - if (Fast)
>>> - return createFastDAGScheduler(IS, Fast);
>>> + if (OptLevel == 0)
>>> + return createFastDAGScheduler(IS, OptLevel);
>>> if (TLI.getSchedulingPreference() ==
>>> TargetLowering::SchedulingForLatency)
>>> - return createTDListDAGScheduler(IS, Fast);
>>> + return createTDListDAGScheduler(IS, OptLevel);
>>> assert(TLI.getSchedulingPreference() ==
>>> TargetLowering::SchedulingForRegPressure && "Unknown sched
>>> type!");
>>> - return createBURRListDAGScheduler(IS, Fast);
>>> + return createBURRListDAGScheduler(IS, OptLevel);
>>> }
>>> }
>>>
>>> @@ -262,13 +262,13 @@
>>> // SelectionDAGISel code
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
>>> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
>>> FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>>> FuncInfo(new FunctionLoweringInfo(TLI)),
>>> CurDAG(new SelectionDAG(TLI, *FuncInfo)),
>>> - SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
>>> + SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>>> GFI(),
>>> - Fast(fast),
>>> + OptLevel(OL),
>>> DAGSize(0)
>>> {}
>>>
>>> @@ -576,9 +576,9 @@
>>> // Run the DAG combiner in pre-legalize mode.
>>> if (TimePassesIsEnabled) {
>>> NamedRegionTimer T("DAG Combining 1", GroupName);
>>> - CurDAG->Combine(Unrestricted, *AA, Fast);
>>> + CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>> } else {
>>> - CurDAG->Combine(Unrestricted, *AA, Fast);
>>> + CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>> }
>>>
>>> DOUT << "Optimized lowered selection DAG:\n";
>>> @@ -608,9 +608,9 @@
>>> // Run the DAG combiner in post-type-legalize mode.
>>> if (TimePassesIsEnabled) {
>>> NamedRegionTimer T("DAG Combining after legalize types",
>>> GroupName);
>>> - CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>> + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>> } else {
>>> - CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>> + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>> }
>>>
>>> DOUT << "Optimized type-legalized selection DAG:\n";
>>> @@ -622,9 +622,9 @@
>>>
>>> if (TimePassesIsEnabled) {
>>> NamedRegionTimer T("DAG Legalization", GroupName);
>>> - CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>> + CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>> } else {
>>> - CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>> + CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>> }
>>>
>>> DOUT << "Legalized selection DAG:\n";
>>> @@ -635,9 +635,9 @@
>>> // Run the DAG combiner in post-legalize mode.
>>> if (TimePassesIsEnabled) {
>>> NamedRegionTimer T("DAG Combining 2", GroupName);
>>> - CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>> + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>> } else {
>>> - CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>> + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>> }
>>>
>>> DOUT << "Optimized legalized selection DAG:\n";
>>> @@ -645,7 +645,7 @@
>>>
>>> if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>>>
>>> - if (!Fast)
>>> + if (OptLevel != 0)
>>> ComputeLiveOutVRegInfo();
>>>
>>> // Third, instruction select all of the operations to machine
>>> code, adding the
>>> @@ -1082,7 +1082,7 @@
>>> RegisterScheduler::setDefault(Ctor);
>>> }
>>>
>>> - return Ctor(this, Fast);
>>> + return Ctor(this, OptLevel);
>>> }
>>>
>>> ScheduleHazardRecognizer
>>> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARM.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
>>> @@ -91,7 +91,7 @@
>>> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
>>> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>>> ARMTargetMachine &TM,
>>> - bool Fast, bool Verbose);
>>> + unsigned OptLevel, bool
>>> Verbose);
>>> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>>> MachineCodeEmitter &MCE);
>>> FunctionPass *createARMLoadStoreOptimizationPass();
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -138,35 +138,37 @@
>>>
>>>
>>> // Pass Pipeline Configuration
>>> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> PM.add(createARMISelDag(*this));
>>> return false;
>>> }
>>>
>>> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel) {
>>> // FIXME: temporarily disabling load / store optimization pass for
>>> Thumb mode.
>>> - if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
>>> + if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>>> PM.add(createARMLoadStoreOptimizationPass());
>>>
>>> - if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
>>> + if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
>>> PM.add(createIfConverterPass());
>>>
>>> PM.add(createARMConstantIslandPass());
>>> return true;
>>> }
>>>
>>> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - bool Verbose, raw_ostream
>>> &Out) {
>>> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> + bool Verbose,
>>> + raw_ostream &Out) {
>>> // Output assembly language.
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>> + PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>
>>> return false;
>>> }
>>>
>>>
>>> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> // FIXME: Move this to TargetJITInfo!
>>> if (DefRelocModel == Reloc::Default)
>>> @@ -177,20 +179,22 @@
>>> if (DumpAsm) {
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> }
>>>
>>> return false;
>>> }
>>>
>>> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> - bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> + bool DumpAsm,
>>> + MachineCodeEmitter
>>> &MCE) {
>>> // Machine code emitter pass for ARM.
>>> PM.add(createARMCodeEmitterPass(*this, MCE));
>>> if (DumpAsm) {
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> }
>>>
>>> return false;
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 19:21:31
>>> 2009
>>> @@ -41,7 +41,7 @@
>>> // set this functions to ctor pointer at startup time if they are
>>> linked in.
>>> typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>> ARMTargetMachine &tm,
>>> - bool fast, bool
>>> verbose);
>>> + unsigned OptLevel, bool
>>> verbose);
>>> static AsmPrinterCtorFn AsmPrinterCtor;
>>>
>>> public:
>>> @@ -69,13 +69,13 @@
>>> virtual const TargetAsmInfo *createTargetAsmInfo() const;
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter &MCE);
>>> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> };
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -80,9 +80,9 @@
>>> /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>>> bool InCPMode;
>>> public:
>>> - ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL),
>>> MCP(NULL),
>>> + explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),
>>> MCP(NULL),
>>> InCPMode(false) {
>>> Subtarget = &TM.getSubtarget<ARMSubtarget>();
>>> }
>>> @@ -1061,8 +1061,8 @@
>>> ///
>>> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>>> ARMTargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel,
>>> bool verbose) {
>>> + return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> namespace {
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
>>> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
>>> @@ -26,7 +26,7 @@
>>> FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>>> FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>>> TargetMachine &TM,
>>> - bool Fast, bool Verbose);
>>> + unsigned OptLevel, bool
>>> Verbose);
>>> FunctionPass *createAlphaPatternInstructionSelector(TargetMachine
>>> &TM);
>>> FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>>> MachineCodeEmitter &MCE);
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -76,31 +76,34 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
>>> + unsigned OptLevel) {
>>> PM.add(createAlphaISelDag(*this));
>>> return false;
>>> }
>>> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
>>> + unsigned OptLevel) {
>>> // Must run branch selection immediately preceding the asm printer
>>> PM.add(createAlphaBranchSelectionPass());
>>> return false;
>>> }
>>> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> bool Verbose,
>>> raw_ostream &Out) {
>>> PM.add(createAlphaLLRPPass(*this));
>>> - PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
>>> + PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>>> return false;
>>> }
>>> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
>>> unsigned OptLevel,
>>> bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> PM.add(createAlphaCodeEmitterPass(*this, MCE));
>>> if (DumpAsm)
>>> - PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
>>> + PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,
>>> true));
>>> return false;
>>> }
>>> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> - bool Fast, bool
>>> DumpAsm,
>>> + unsigned OptLevel,
>>> bool DumpAsm,
>>> MachineCodeEmitter
>>> &MCE) {
>>> - return addCodeEmitter(PM, Fast, DumpAsm, MCE);
>>> + return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -58,13 +58,13 @@
>>> static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter &MCE);
>>> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> };
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -36,9 +36,9 @@
>>> /// Unique incrementer for label values for referencing Global
>>> values.
>>> ///
>>>
>>> - AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(o, tm, T, F, V) {}
>>> + explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(o, tm, T, OL, V) {}
>>>
>>> virtual const char *getPassName() const {
>>> return "Alpha Assembly Printer";
>>> @@ -68,8 +68,9 @@
>>> ///
>>> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>>> TargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel,
>>> + bool verbose) {
>>> + return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> #include "AlphaGenAsmWriter.inc"
>>>
>>> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -3587,7 +3587,7 @@
>>> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &o,
>>> CodeGenFileType
>>> FileType,
>>> - bool Fast) {
>>> + unsigned OptLevel) {
>>> if (FileType != TargetMachine::AssemblyFile) return true;
>>>
>>> PM.add(createGCLoweringPass());
>>>
>>> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -27,7 +27,8 @@
>>>
>>> virtual bool WantsWholeFile() const { return true; }
>>> virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>> &Out,
>>> - CodeGenFileType FileType,
>>> bool Fast);
>>> + CodeGenFileType FileType,
>>> + unsigned OptLevel);
>>>
>>> // This class always works, but must be requested explicitly on
>>> // llc command line.
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -48,9 +48,9 @@
>>> class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>>> std::set<std::string> FnStubs, GVStubs;
>>> public:
>>> - SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V) :
>>> - AsmPrinter(O, TM, T, F, V) {}
>>> + explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V) :
>>> + AsmPrinter(O, TM, T, OL, V) {}
>>>
>>> virtual const char *getPassName() const {
>>> return "STI CBEA SPU Assembly Printer";
>>> @@ -615,6 +615,6 @@
>>> ///
>>> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>>> SPUTargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel, bool
>>> verbose) {
>>> + return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
>>> @@ -25,7 +25,7 @@
>>> FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>>> FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>>> SPUTargetMachine &tm,
>>> - bool fast, bool verbose);
>>> + unsigned OptLevel, bool
>>> verbose);
>>>
>>> /*--== Utility functions/predicates/etc used all over the place: --
>>> ==*/
>>> //! Predicate test for a signed 10-bit value
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -81,15 +81,17 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> bool
>>> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
>>> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel)
>>> {
>>> // Install an instruction selector.
>>> PM.add(createSPUISelDag(*this));
>>> return false;
>>> }
>>>
>>> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - bool Verbose, raw_ostream
>>> &Out) {
>>> - PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
>>> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> + bool Verbose,
>>> + raw_ostream &Out) {
>>> + PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>>> return false;
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -83,9 +83,9 @@
>>> }
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /
>>> *Fast*/,
>>> - bool /*Verbose*/, raw_ostream
>>> &Out);
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> + bool Verbose, raw_ostream &Out);
>>> };
>>>
>>> } // end namespace llvm
>>>
>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -1995,7 +1995,7 @@
>>> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &o,
>>> CodeGenFileType
>>> FileType,
>>> - bool Fast) {
>>> + unsigned OptLevel) {
>>> if (FileType != TargetMachine::AssemblyFile) return true;
>>> PM.add(new CppWriter(o));
>>> return false;
>>>
>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -29,7 +29,8 @@
>>>
>>> virtual bool WantsWholeFile() const { return true; }
>>> virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>> &Out,
>>> - CodeGenFileType FileType,
>>> bool Fast);
>>> + CodeGenFileType FileType,
>>> + unsigned OptLevel);
>>>
>>> // This class always works, but shouldn't be the default in most
>>> cases.
>>> static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -37,9 +37,9 @@
>>> class IA64AsmPrinter : public AsmPrinter {
>>> std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>>> public:
>>> - IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(O, TM, T, F, V) {}
>>> + explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(O, TM, T, OL, V) {}
>>>
>>> virtual const char *getPassName() const {
>>> return "IA64 Assembly Printer";
>>> @@ -370,6 +370,7 @@
>>> ///
>>> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>>> IA64TargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel,
>>> + bool verbose) {
>>> + return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
>>> @@ -37,7 +37,7 @@
>>> ///
>>> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>>> IA64TargetMachine &tm,
>>> - bool fast, bool verbose);
>>> + unsigned OptLevel, bool
>>> verbose);
>>>
>>> } // End llvm namespace
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -72,19 +72,21 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLEvel){
>>> PM.add(createIA64DAGToDAGInstructionSelector(*this));
>>> return false;
>>> }
>>>
>>> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> // Make sure everything is bundled happily
>>> PM.add(createIA64BundlingPass(*this));
>>> return true;
>>> }
>>> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> - bool Verbose,
>>> raw_ostream &Out) {
>>> - PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
>>> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> + bool Verbose,
>>> + raw_ostream &Out) {
>>> + PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>>> return false;
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -51,9 +51,9 @@
>>> static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> };
>>> } // End llvm namespace
>>>
>>> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
>>> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -35,7 +35,8 @@
>>>
>>> virtual bool WantsWholeFile() const { return true; }
>>> virtual bool addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &Out,
>>> - CodeGenFileType FileType,
>>> bool Fast);
>>> + CodeGenFileType FileType,
>>> + unsigned OptLevel);
>>>
>>> // This class always works, but shouldn't be the default in most
>>> cases.
>>> static unsigned getModuleMatchQuality(const Module &M) { return
>>> 1; }
>>> @@ -1662,7 +1663,8 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &o,
>>> - CodeGenFileType FileType,
>>> bool Fast)
>>> + CodeGenFileType FileType,
>>> + unsigned OptLevel)
>>> {
>>> if (FileType != TargetMachine::AssemblyFile) return true;
>>> MSILWriter* Writer = new MSILWriter(o);
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -49,9 +49,9 @@
>>> class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>>> const MipsSubtarget *Subtarget;
>>> public:
>>> - MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(O, TM, T, F, V) {
>>> + explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(O, TM, T, OL, V) {
>>> Subtarget = &TM.getSubtarget<MipsSubtarget>();
>>> }
>>>
>>> @@ -91,8 +91,8 @@
>>> /// regardless of whether the function is in SSA form.
>>> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>>> MipsTargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel,
>>> bool verbose) {
>>> + return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/Mips.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
>>> @@ -25,7 +25,7 @@
>>> FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>>> FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>>> MipsTargetMachine &TM,
>>> - bool Fast, bool Verbose);
>>> + unsigned OptLevel, bool
>>> Verbose);
>>> } // end namespace llvm;
>>>
>>> // Defines symbolic names for Mips registers. This defines a
>>> mapping from
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -105,7 +105,7 @@
>>> // Install an instruction selector pass using
>>> // the ISelDag to gen Mips code.
>>> bool MipsTargetMachine::
>>> -addInstSelector(PassManagerBase &PM, bool Fast)
>>> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
>>> {
>>> PM.add(createMipsISelDag(*this));
>>> return false;
>>> @@ -115,7 +115,7 @@
>>> // machine code is emitted. return true if -print-machineinstrs
>>> should
>>> // print out the code after the passes.
>>> bool MipsTargetMachine::
>>> -addPreEmitPass(PassManagerBase &PM, bool Fast)
>>> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
>>> {
>>> PM.add(createMipsDelaySlotFillerPass(*this));
>>> return true;
>>> @@ -124,10 +124,10 @@
>>> // Implements the AssemblyEmitter for the target. Must return
>>> // true if AssemblyEmitter is supported
>>> bool MipsTargetMachine::
>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>>> bool Verbose, raw_ostream &Out)
>>> {
>>> // Output assembly language.
>>> - PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
>>> + PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
>>> return false;
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,9 +57,9 @@
>>> static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> };
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
>>> @@ -75,7 +75,7 @@
>>> FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>>> FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>>> PIC16TargetMachine &TM,
>>> - bool Fast, bool Verbose);
>>> + unsigned OptLevel, bool
>>> Verbose);
>>> } // end namespace llvm;
>>>
>>> // Defines symbolic names for PIC16 registers. This defines a
>>> mapping from
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -161,8 +161,9 @@
>>> ///
>>> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>>> PIC16TargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> - return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + unsigned OptLevel,
>>> + bool verbose) {
>>> + return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int
>>> opNum) {
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -24,9 +24,9 @@
>>>
>>> namespace llvm {
>>> struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
>>> - PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(O, TM, T, F, V) {
>>> + explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(O, TM, T, OL, V) {
>>> CurBank = "";
>>> FunctionLabelBegin = '@';
>>> IsRomData = false;
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -55,17 +55,18 @@
>>> return new PIC16TargetAsmInfo(*this);
>>> }
>>>
>>> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
>>> + unsigned OptLevel) {
>>> // Install an instruction selector.
>>> PM.add(createPIC16ISelDag(*this));
>>> return false;
>>> }
>>>
>>> bool PIC16TargetMachine::
>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool
>>> Verbose,
>>> raw_ostream &Out) {
>>> // Output assembly language.
>>> - PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
>>> + PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>>> return false;
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,8 +57,8 @@
>>> return const_cast<PIC16TargetLowering*>(&TLInfo);
>>> }
>>>
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> }; // PIC16TargetMachine.
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -54,9 +54,9 @@
>>> StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>>> const PPCSubtarget &Subtarget;
>>> public:
>>> - PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : AsmPrinter(O, TM, T, F, V),
>>> + explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + : AsmPrinter(O, TM, T, OL, V),
>>> Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>>>
>>> virtual const char *getPassName() const {
>>> @@ -297,9 +297,9 @@
>>> DwarfWriter *DW;
>>> MachineModuleInfo *MMI;
>>> public:
>>> - PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>>> + explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine
>>> &TM,
>>> + const TargetAsmInfo *T, unsigned
>>> OL, bool V)
>>> + : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>>>
>>> virtual const char *getPassName() const {
>>> return "Linux PPC Assembly Printer";
>>> @@ -326,9 +326,9 @@
>>> MachineModuleInfo *MMI;
>>> raw_ostream &OS;
>>> public:
>>> - PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>> - const TargetAsmInfo *T, bool F, bool V)
>>> - : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
>>> + explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine
>>> &TM,
>>> + const TargetAsmInfo *T, unsigned
>>> OL, bool V)
>>> + : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>>>
>>> virtual const char *getPassName() const {
>>> return "Darwin PPC Assembly Printer";
>>> @@ -1176,13 +1176,15 @@
>>> ///
>>> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>>> PPCTargetMachine &tm,
>>> - bool fast, bool
>>> verbose) {
>>> + unsigned OptLevel, bool
>>> verbose) {
>>> const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>>>
>>> if (Subtarget->isDarwin()) {
>>> - return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> fast, verbose);
>>> + return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> + OptLevel, verbose);
>>> } else {
>>> - return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> fast, verbose);
>>> + return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> + OptLevel, verbose);
>>> }
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
>>> @@ -28,7 +28,7 @@
>>> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
>>> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>>> PPCTargetMachine &TM,
>>> - bool Fast, bool Verbose);
>>> + unsigned OptLevel, bool
>>> Verbose);
>>> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>>> MachineCodeEmitter &MCE);
>>> } // end namespace llvm;
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -129,29 +129,31 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> // Install an instruction selector.
>>> PM.add(createPPCISelDag(*this));
>>> return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel) {
>>>
>>> // Must run branch selection immediately preceding the asm printer.
>>> PM.add(createPPCBranchSelectionPass());
>>> return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - bool Verbose, raw_ostream
>>> &Out) {
>>> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + unsigned OptLevel,
>>> + bool Verbose,
>>> + raw_ostream &Out) {
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>> + PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>
>>> return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> // The JIT should use the static relocation model in ppc32 mode,
>>> PIC in ppc64.
>>> // FIXME: This should be moved to TargetJITInfo!!
>>> @@ -176,20 +178,20 @@
>>> if (DumpAsm) {
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> }
>>>
>>> return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> unsigned OptLevel,
>>> bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> // Machine code emitter pass for PowerPC.
>>> PM.add(createPPCCodeEmitterPass(*this, MCE));
>>> if (DumpAsm) {
>>> assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> if (AsmPrinterCtor)
>>> - PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> }
>>>
>>> return false;
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -46,7 +46,7 @@
>>> // set this functions to ctor pointer at startup time if they are
>>> linked in.
>>> typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>> PPCTargetMachine &tm,
>>> - bool fast, bool
>>> verbose);
>>> + unsigned OptLevel, bool
>>> verbose);
>>> static AsmPrinterCtorFn AsmPrinterCtor;
>>>
>>> public:
>>> @@ -76,13 +76,13 @@
>>> }
>>>
>>> // Pass Pipeline Configuration
>>> - virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool Verbose, raw_ostream &Out);
>>> - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter &MCE);
>>> - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> virtual bool getEnableTailMergeDefault() const;
>>> };
>>>
>>> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =========================================
> ...
>
> [Message clipped]
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