[llvm-commits] [llvm] r70176 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Transforms/IndVarSimplify/avoid-i0.ll
Dan Gohman
gohman at apple.com
Sun Apr 26 18:41:10 PDT 2009
Author: djg
Date: Sun Apr 26 20:41:10 2009
New Revision: 70176
URL: http://llvm.org/viewvc/llvm-project?rev=70176&view=rev
Log:
Handle ands with ~0 correctly too. This fixes PR4052.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
llvm/trunk/test/Transforms/IndVarSimplify/avoid-i0.ll
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70176&r1=70175&r2=70176&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Sun Apr 26 20:41:10 2009
@@ -1756,6 +1756,8 @@
if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
if (CI->isNullValue())
return getSCEV(U->getOperand(1));
+ if (CI->isAllOnesValue())
+ return getSCEV(U->getOperand(0));
const APInt &A = CI->getValue();
unsigned Ones = A.countTrailingOnes();
if (APIntOps::isMask(Ones, A))
Modified: llvm/trunk/test/Transforms/IndVarSimplify/avoid-i0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/avoid-i0.ll?rev=70176&r1=70175&r2=70176&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/avoid-i0.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/avoid-i0.ll Sun Apr 26 20:41:10 2009
@@ -1,4 +1,5 @@
; RUN: llvm-as < %s | opt -indvars
+; PR4052
; PR4054
; Don't treat an and with 0 as a mask (trunc+zext).
@@ -21,3 +22,105 @@
%0 = and i8 0, 0 ; <i8> [#uses=1]
br label %bb
}
+
+ at x = common global i32 0 ; <i32*> [#uses=1]
+
+define signext i8 @safe_sub_func_int32_t_s_s(i32 %_si1, i8 signext %_si2) nounwind {
+entry:
+ %_si1_addr = alloca i32 ; <i32*> [#uses=3]
+ %_si2_addr = alloca i8 ; <i8*> [#uses=3]
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %_si1, i32* %_si1_addr
+ store i8 %_si2, i8* %_si2_addr
+ %1 = load i8* %_si2_addr, align 1 ; <i8> [#uses=1]
+ %2 = sext i8 %1 to i32 ; <i32> [#uses=1]
+ %3 = load i32* %_si1_addr, align 4 ; <i32> [#uses=1]
+ %4 = xor i32 %2, %3 ; <i32> [#uses=1]
+ %5 = load i8* %_si2_addr, align 1 ; <i8> [#uses=1]
+ %6 = sext i8 %5 to i32 ; <i32> [#uses=1]
+ %7 = sub i32 7, %6 ; <i32> [#uses=1]
+ %8 = load i32* %_si1_addr, align 4 ; <i32> [#uses=1]
+ %9 = shl i32 %8, %7 ; <i32> [#uses=1]
+ %10 = and i32 %4, %9 ; <i32> [#uses=1]
+ %11 = icmp slt i32 %10, 0 ; <i1> [#uses=1]
+ %12 = zext i1 %11 to i32 ; <i32> [#uses=1]
+ store i32 %12, i32* %0, align 4
+ %13 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %13, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ %retval12 = trunc i32 %retval1 to i8 ; <i8> [#uses=1]
+ ret i8 %retval12
+}
+
+define i32 @safe_sub_func_uint64_t_u_u(i32 %_ui1, i32 %_ui2) nounwind {
+entry:
+ %_ui1_addr = alloca i32 ; <i32*> [#uses=2]
+ %_ui2_addr = alloca i32 ; <i32*> [#uses=1]
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %_ui1, i32* %_ui1_addr
+ store i32 %_ui2, i32* %_ui2_addr
+ %1 = load i32* %_ui1_addr, align 4 ; <i32> [#uses=1]
+ %2 = sub i32 %1, 1 ; <i32> [#uses=1]
+ store i32 %2, i32* %0, align 4
+ %3 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %3, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
+
+define void @int87(i8 signext %p_48, i8 signext %p_49) nounwind {
+entry:
+ %p_48_addr = alloca i8 ; <i8*> [#uses=1]
+ %p_49_addr = alloca i8 ; <i8*> [#uses=1]
+ %l_52 = alloca i32 ; <i32*> [#uses=7]
+ %vol.0 = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i8 %p_48, i8* %p_48_addr
+ store i8 %p_49, i8* %p_49_addr
+ br label %bb4
+
+bb: ; preds = %bb4
+ %0 = volatile load i32* @x, align 4 ; <i32> [#uses=1]
+ store i32 %0, i32* %vol.0, align 4
+ store i32 0, i32* %l_52, align 4
+ br label %bb2
+
+bb1: ; preds = %bb2
+ %1 = load i32* %l_52, align 4 ; <i32> [#uses=1]
+ %2 = call i32 @safe_sub_func_uint64_t_u_u(i32 %1, i32 1) nounwind ; <i32> [#uses=1]
+ store i32 %2, i32* %l_52, align 4
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb
+ %3 = load i32* %l_52, align 4 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %bb1, label %bb3
+
+bb3: ; preds = %bb2
+ %5 = load i32* %l_52, align 4 ; <i32> [#uses=1]
+ %6 = call signext i8 @safe_sub_func_int32_t_s_s(i32 %5, i8 signext 1) nounwind ; <i8> [#uses=1]
+ %7 = sext i8 %6 to i32 ; <i32> [#uses=1]
+ store i32 %7, i32* %l_52, align 4
+ br label %bb4
+
+bb4: ; preds = %bb3, %entry
+ %8 = load i32* %l_52, align 4 ; <i32> [#uses=1]
+ %9 = icmp ne i32 %8, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb, label %bb5
+
+bb5: ; preds = %bb4
+ br label %return
+
+return: ; preds = %bb5
+ ret void
+}
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