[llvm-commits] [llvm] r68961 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetInstrInfo.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/DAGISelEmitter.cpp utils/TableGen/InstrInfoEmitter.cpp utils/TableGen/RegisterInfoEmitter.cpp

[Jakob Stoklund Olesen]

On 13/04/2009, at 21.49, Dan Gohman wrote:

>
> On Apr 13, 2009, at 9:23 AM, Jakob Stoklund Olesen wrote:
>> Very nice. I wonder, is it necessary to restrict to subclasses? My
>> Blackfin target has disjoint register classes, but I can still copy
>> between them. COPY_TO_REGCLASS?
>
> With the register class enhancement changes that accompanied this
> change, the code that expands post-isel SDNodes into MachineInstrs
> now automatically inserts copies when needed to bridge between
> different register classes.  COPY_TO_SUBCLASS is only needed in
> situations where the the register class of the virtual registers
> needs to be something other than what the instruction patterns
> indicate they require.

Right, like the EXTRACT_SUBREG patterns in X86.

> Can you give an example of a pattern where this would be used?

Not a really good one, it just seemed like an unnecessary restriction.

On Blackfin, I have register classes D for data, P for pointers. The  
classes are disjoint. I can only access subregisters in the D class,  
so a pattern fragment like this is not unthinkable:

(EXTRACT_SUBREG (COPY_TO_REGCLASS P:$ptr, D), bfin_subreg_lo16)

EXTRACT_SUBREG doesn't know what regclass to expect, so the automatic  
copies won't work.

I don't actually have any patterns like that, so it is no big deal.