[llvm-commits] [llvm] r68961 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetInstrInfo.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/DAGISelEmitter.cpp utils/TableGen/InstrInfoEmitter.cpp utils/TableGen/RegisterInfoEmitter.cpp

[Jakob Stoklund Olesen]

On 13/04/2009, at 17.38, Dan Gohman wrote:

> Author: djg
> Date: Mon Apr 13 10:38:05 2009
> New Revision: 68961
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68961&view=rev
> Log:
> Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
> This will be used to replace things like X86's MOV32to32_.

Very nice. I wonder, is it necessary to restrict to subclasses? My  
Blackfin target has disjoint register classes, but I can still copy  
between them. COPY_TO_REGCLASS?

> Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
> in the presense of subregister superclasses and subclasses. It
> can now cope with the definition of a virtual register being in
> a subclass of a use.

Great! This is better than my own patch.

> Re-introduce the code for recording register superreg classes and
> subreg classes. This is needed because when subreg extracts and
> inserts get coalesced away, the virtual registers are left in
> the correct subclass.

Thanks!