[llvm-commits] [llvm] r68671 - /llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

[Sanjiv Gupta]

Author: sgupta
Date: Wed Apr  8 23:03:43 2009
New Revision: 68671

URL: http://llvm.org/viewvc/llvm-project?rev=68671&view=rev
Log:
r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=68671&r1=68670&r2=68671&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Apr  8 23:03:43 2009
@@ -1359,21 +1359,26 @@
     // Put one value on stack.
     SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
     
+    // ADDC and ADDE produces two results.
     SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
 
+    // ADDE has three operands, the last one is a flag.
     if (Op.getOpcode() == ISD::ADDE)
       return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
                          NewVal, Op.getOperand(2));
-    else
+    // ADDC has two operands.
+    else if (Op.getOpcode() == ISD::ADDC)
       return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
                          NewVal);
+    // ADD it is. It produces only one result.
+    else
+      return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
+                         NewVal);
   }
-  else if (Op.getOpcode() == ISD::ADD) {
+  else if (Op.getOpcode() == ISD::ADD)
     return Op;
-  }
-  else {
+  else
     return SDValue();
-  }
 }
 
 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {