[llvm-commits] [llvm] r68552 - in /llvm/trunk: lib/Target/X86/ lib/Target/X86/AsmPrinter/ test/CodeGen/X86/
Bill Wendling
isanbard at gmail.com
Tue Apr 7 15:17:51 PDT 2009
Rafael,
This is causing a self-hosting LLVM to fail to build:
llvm[1]: Compiling IsInf.cpp for Release build
if /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~dst/Developer/usr/bin/llvm-g++-4.2
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support
-D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS
-O2 -fno-exceptions -fno-common -Woverloaded-virtual -m32 -pedantic
-Wall -W -Wwrite-strings -Wno-long-long -Wunused -Wno-unused-parameter
-fstrict-aliasing -Wstrict-aliasing -c -MMD -MP -MF
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp"
-MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o"
-MT "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d"
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp
-o /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o
; \
then /bin/mv -f
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp"
"/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d";
else /bin/rm "/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.d.tmp";
exit 1; fi
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:41:3:
error: #error "Don't know how to get isinf()"
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:
In function 'int llvm::IsInf(float)':
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:46:
error: 'isinf' was not declared in this scope
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:
In function 'int llvm::IsInf(double)':
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/lib/Support/IsInf.cpp:47:
error: 'isinf' was not declared in this scope
make[1]: *** [/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.sh.build/lib/Support/Release/IsInf.o]
Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [all] Error 1
Please investigate. Thanks!
-bw
On Tue, Apr 7, 2009 at 2:37 PM, Rafael Espindola
<rafael.espindola at gmail.com> wrote:
> Author: rafael
> Date: Tue Apr 7 16:37:46 2009
> New Revision: 68552
>
> URL: http://llvm.org/viewvc/llvm-project?rev=68552&view=rev
> Log:
> Reduce code duplication on the TLS implementation.
> This introduces a small regression on the generated code
> quality in the case we are just computing addresses, not
> loading values.
>
> Will work on it and on X86-64 support.
>
>
> Modified:
> llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
> llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
> llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> llvm/trunk/lib/Target/X86/X86FastISel.cpp
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/X86/X86Instr64bit.td
> llvm/trunk/lib/Target/X86/X86InstrBuilder.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> llvm/trunk/test/CodeGen/X86/tls10.ll
> llvm/trunk/test/CodeGen/X86/tls2.ll
> llvm/trunk/test/CodeGen/X86/tls6.ll
> llvm/trunk/test/CodeGen/X86/tls8.ll
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Apr 7 16:37:46 2009
> @@ -566,9 +566,8 @@
> }
> }
>
> -void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> - const char *Modifier){
> - assert(isMem(MI, Op) && "Invalid memory reference!");
> +void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + const char *Modifier){
> MachineOperand BaseReg = MI->getOperand(Op);
> MachineOperand IndexReg = MI->getOperand(Op+2);
> const MachineOperand &DispSpec = MI->getOperand(Op+3);
> @@ -611,6 +610,17 @@
> }
> }
>
> +void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> + const char *Modifier){
> + assert(isMem(MI, Op) && "Invalid memory reference!");
> + MachineOperand Segment = MI->getOperand(Op+4);
> + if (Segment.getReg()) {
> + printOperand(MI, Op+4, Modifier);
> + O << ':';
> + }
> + printLeaMemReference(MI, Op, Modifier);
> +}
> +
> void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
> const MachineBasicBlock *MBB) const {
> if (!TAI->getSetDirective())
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr 7 16:37:46 2009
> @@ -93,8 +93,14 @@
> void printf128mem(const MachineInstr *MI, unsigned OpNo) {
> printMemReference(MI, OpNo);
> }
> + void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
> + printLeaMemReference(MI, OpNo);
> + }
> + void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
> + printLeaMemReference(MI, OpNo);
> + }
> void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
> - printMemReference(MI, OpNo, "subreg64");
> + printLeaMemReference(MI, OpNo, "subreg64");
> }
>
> bool printAsmMRegister(const MachineOperand &MO, const char Mode);
> @@ -107,6 +113,8 @@
> void printSSECC(const MachineInstr *MI, unsigned Op);
> void printMemReference(const MachineInstr *MI, unsigned Op,
> const char *Modifier=NULL);
> + void printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + const char *Modifier=NULL);
> void printPICJumpTableSetLabel(unsigned uid,
> const MachineBasicBlock *MBB) const;
> void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Tue Apr 7 16:37:46 2009
> @@ -271,10 +271,9 @@
> }
> }
>
> -void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> - const char *Modifier) {
> - assert(isMem(MI, Op) && "Invalid memory reference!");
> -
> +void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
> + unsigned Op,
> + const char *Modifier) {
> const MachineOperand &BaseReg = MI->getOperand(Op);
> int ScaleVal = MI->getOperand(Op+1).getImm();
> const MachineOperand &IndexReg = MI->getOperand(Op+2);
> @@ -317,6 +316,17 @@
> O << "]";
> }
>
> +void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
> + const char *Modifier) {
> + assert(isMem(MI, Op) && "Invalid memory reference!");
> + MachineOperand Segment = MI->getOperand(Op+4);
> + if (Segment.getReg()) {
> + printOperand(MI, Op+4, Modifier);
> + O << ':';
> + }
> + printLeaMemReference(MI, Op, Modifier);
> +}
> +
> void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
> const MachineBasicBlock *MBB) const {
> if (!TAI->getSetDirective())
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue Apr 7 16:37:46 2009
> @@ -88,9 +88,17 @@
> O << "XMMWORD PTR ";
> printMemReference(MI, OpNo);
> }
> + void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
> + O << "DWORD PTR ";
> + printLeaMemReference(MI, OpNo);
> + }
> + void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
> + O << "QWORD PTR ";
> + printLeaMemReference(MI, OpNo);
> + }
> void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
> O << "QWORD PTR ";
> - printMemReference(MI, OpNo, "subreg64");
> + printLeaMemReference(MI, OpNo, "subreg64");
> }
>
> bool printAsmMRegister(const MachineOperand &MO, const char Mode);
> @@ -103,6 +111,8 @@
> void printSSECC(const MachineInstr *MI, unsigned Op);
> void printMemReference(const MachineInstr *MI, unsigned Op,
> const char *Modifier=NULL);
> + void printLeaMemReference(const MachineInstr *MI, unsigned Op,
> + const char *Modifier=NULL);
> void printPICJumpTableSetLabel(unsigned uid,
> const MachineBasicBlock *MBB) const;
> void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Apr 7 16:37:46 2009
> @@ -533,23 +533,6 @@
> case X86::DWARF_LOC:
> case X86::FP_REG_KILL:
> break;
> - case X86::TLS_tp: {
> - MCE.emitByte(BaseOpcode);
> - unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
> - MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
> - emitConstant(0, 4);
> - break;
> - }
> - case X86::TLS_gs_ri: {
> - MCE.emitByte(BaseOpcode);
> - unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
> - MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
> - GlobalValue* GV = MI.getOperand(1).getGlobal();
> - unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
> - : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
> - emitGlobalAddress(GV, rt);
> - break;
> - }
> case X86::MOVPC32r: {
> // This emits the "call" portion of this pseudo instruction.
> MCE.emitByte(BaseOpcode);
> @@ -661,13 +644,21 @@
> break;
>
> case X86II::MRMSrcMem: {
> - intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
> + // FIXME: Maybe lea should have its own form?
> + int AddrOperands;
> + if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
> + Opcode == X86::LEA16r || Opcode == X86::LEA32r)
> + AddrOperands = X86AddrNumOperands - 1; // No segment register
> + else
> + AddrOperands = X86AddrNumOperands;
> +
> + intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
> X86InstrInfo::sizeOfImm(Desc) : 0;
>
> MCE.emitByte(BaseOpcode);
> emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
> PCAdj);
> - CurOp += X86AddrNumOperands + 1;
> + CurOp += AddrOperands + 1;
> if (CurOp != NumOps)
> emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
> break;
>
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Apr 7 16:37:46 2009
> @@ -1490,7 +1490,7 @@
> else
> Opc = X86::LEA64r;
> unsigned ResultReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> return ResultReg;
> }
> return 0;
> @@ -1535,7 +1535,7 @@
> unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
> TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
> unsigned ResultReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> return ResultReg;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr 7 16:37:46 2009
> @@ -69,6 +69,7 @@
> unsigned Scale;
> SDValue IndexReg;
> int32_t Disp;
> + SDValue Segment;
> GlobalValue *GV;
> Constant *CP;
> const char *ES;
> @@ -77,7 +78,7 @@
>
> X86ISelAddressMode()
> : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
> - GV(0), CP(0), ES(0), JT(-1), Align(0) {
> + Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) {
> }
>
> bool hasSymbolicDisplacement() const {
> @@ -159,20 +160,25 @@
> SDNode *Select(SDValue N);
> SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
>
> + bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
> + bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
> bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
> unsigned Depth = 0);
> bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
> bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
> - SDValue &Scale, SDValue &Index, SDValue &Disp);
> + SDValue &Scale, SDValue &Index, SDValue &Disp,
> + SDValue &Segment);
> bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
> SDValue &Scale, SDValue &Index, SDValue &Disp);
> bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
> SDValue N, SDValue &Base, SDValue &Scale,
> SDValue &Index, SDValue &Disp,
> + SDValue &Segment,
> SDValue &InChain, SDValue &OutChain);
> bool TryFoldLoad(SDValue P, SDValue N,
> SDValue &Base, SDValue &Scale,
> - SDValue &Index, SDValue &Disp);
> + SDValue &Index, SDValue &Disp,
> + SDValue &Segment);
> void PreprocessForRMW();
> void PreprocessForFPConvert();
>
> @@ -186,7 +192,7 @@
>
> inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
> SDValue &Scale, SDValue &Index,
> - SDValue &Disp) {
> + SDValue &Disp, SDValue &Segment) {
> Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
> CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
> AM.Base.Reg;
> @@ -205,6 +211,11 @@
> Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
> else
> Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
> +
> + if (AM.Segment.getNode())
> + Segment = AM.Segment;
> + else
> + Segment = CurDAG->getRegister(0, MVT::i32);
> }
>
> /// getI8Imm - Return a target constant with the specified value, of type
> @@ -726,6 +737,33 @@
> EmitSpecialCodeForMain(BB, MF.getFrameInfo());
> }
>
> +
> +bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
> + X86ISelAddressMode &AM) {
> + assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
> + SDValue Segment = N.getOperand(0);
> +
> + if (AM.Segment.getNode() == 0) {
> + AM.Segment = Segment;
> + return false;
> + }
> +
> + return true;
> +}
> +
> +bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
> + // This optimization is valid because the GNU TLS model defines that
> + // gs:0 (or fs:0 on X86-64) contains its own address.
> + // For more information see http://people.redhat.com/drepper/tls.pdf
> +
> + SDValue Address = N.getOperand(1);
> + if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
> + !MatchSegmentBaseAddress (Address, AM))
> + return false;
> +
> + return true;
> +}
> +
> /// MatchAddress - Add the specified node to the specified addressing mode,
> /// returning true if it cannot be done. This just pattern matches for the
> /// addressing mode.
> @@ -761,6 +799,11 @@
> break;
> }
>
> + case X86ISD::SegmentBaseAddress:
> + if (!MatchSegmentBaseAddress(N, AM))
> + return false;
> + break;
> +
> case X86ISD::Wrapper: {
> DOUT << "Wrapper: 64bit " << is64Bit;
> DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
> @@ -807,6 +850,11 @@
> break;
> }
>
> + case ISD::LOAD:
> + if (!MatchLoad(N, AM))
> + return false;
> + break;
> +
> case ISD::FrameIndex:
> if (AM.BaseType == X86ISelAddressMode::RegBase
> && AM.Base.Reg.getNode() == 0) {
> @@ -1034,7 +1082,7 @@
> /// match by reference.
> bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
> SDValue &Scale, SDValue &Index,
> - SDValue &Disp) {
> + SDValue &Disp, SDValue &Segment) {
> X86ISelAddressMode AM;
> bool Done = false;
> if (AvoidDupAddrCompute && !N.hasOneUse()) {
> @@ -1069,7 +1117,7 @@
> if (!AM.IndexReg.getNode())
> AM.IndexReg = CurDAG->getRegister(0, VT);
>
> - getAddressOperands(AM, Base, Scale, Index, Disp);
> + getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> return true;
> }
>
> @@ -1079,7 +1127,8 @@
> bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
> SDValue N, SDValue &Base,
> SDValue &Scale, SDValue &Index,
> - SDValue &Disp, SDValue &InChain,
> + SDValue &Disp, SDValue &Segment,
> + SDValue &InChain,
> SDValue &OutChain) {
> if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
> InChain = N.getOperand(0).getValue(1);
> @@ -1088,7 +1137,7 @@
> N.hasOneUse() &&
> IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
> LoadSDNode *LD = cast<LoadSDNode>(InChain);
> - if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
> + if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
> return false;
> OutChain = LD->getChain();
> return true;
> @@ -1105,7 +1154,7 @@
> N.getOperand(0).getOperand(0).hasOneUse()) {
> // Okay, this is a zero extending load. Fold it.
> LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
> - if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
> + if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
> return false;
> OutChain = LD->getChain();
> InChain = SDValue(LD, 1);
> @@ -1124,6 +1173,11 @@
> if (MatchAddress(N, AM))
> return false;
>
> + //Is it better to set AM.Segment before calling MatchAddress to
> + //prevent it from adding a segment?
> + if (AM.Segment.getNode())
> + return false;
> +
> MVT VT = N.getValueType();
> unsigned Complexity = 0;
> if (AM.BaseType == X86ISelAddressMode::RegBase)
> @@ -1162,7 +1216,8 @@
> Complexity++;
>
> if (Complexity > 2) {
> - getAddressOperands(AM, Base, Scale, Index, Disp);
> + SDValue Segment;
> + getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> return true;
> }
> return false;
> @@ -1170,11 +1225,12 @@
>
> bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
> SDValue &Base, SDValue &Scale,
> - SDValue &Index, SDValue &Disp) {
> + SDValue &Index, SDValue &Disp,
> + SDValue &Segment) {
> if (ISD::isNON_EXTLoad(N.getNode()) &&
> N.hasOneUse() &&
> IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
> - return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
> + return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
> return false;
> }
>
> @@ -1230,11 +1286,11 @@
> SDValue In1 = Node->getOperand(1);
> SDValue In2L = Node->getOperand(2);
> SDValue In2H = Node->getOperand(3);
> - SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
> + SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
> return NULL;
> SDValue LSI = Node->getOperand(4); // MemOperand
> - const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
> + const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
> return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
> MVT::i32, MVT::i32, MVT::Other, Ops,
> array_lengthof(Ops));
> @@ -1316,11 +1372,11 @@
> case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
> }
>
> - SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
> + SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> // multiplty is commmutative
> if (!foldedLoad) {
> - foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
> + foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> if (foldedLoad)
> std::swap(N0, N1);
> }
> @@ -1329,7 +1385,8 @@
> N0, SDValue()).getValue(1);
>
> if (foldedLoad) {
> - SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
> + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
> + InFlag };
> SDNode *CNode =
> CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
> array_lengthof(Ops));
> @@ -1438,17 +1495,17 @@
> break;
> }
>
> - SDValue Tmp0, Tmp1, Tmp2, Tmp3;
> - bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
> + SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
> + bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
> bool signBitIsZero = CurDAG->SignBitIsZero(N0);
>
> SDValue InFlag;
> if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
> // Special case for div8, just use a move with zero extension to AX to
> // clear the upper 8 bits (AH).
> - SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
> - if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
> - SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
> + SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
> + if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
> + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
> Move =
> SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
> MVT::Other, Ops,
> @@ -1480,7 +1537,8 @@
> }
>
> if (foldedLoad) {
> - SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
> + SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
> + InFlag };
> SDNode *CNode =
> CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
> array_lengthof(Ops));
> @@ -1649,13 +1707,13 @@
> bool X86DAGToDAGISel::
> SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> std::vector<SDValue> &OutOps) {
> - SDValue Op0, Op1, Op2, Op3;
> + SDValue Op0, Op1, Op2, Op3, Op4;
> switch (ConstraintCode) {
> case 'o': // offsetable ??
> case 'v': // not offsetable ??
> default: return true;
> case 'm': // memory
> - if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
> + if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
> return true;
> break;
> }
> @@ -1664,6 +1722,7 @@
> OutOps.push_back(Op1);
> OutOps.push_back(Op2);
> OutOps.push_back(Op3);
> + OutOps.push_back(Op4);
> return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr 7 16:37:46 2009
> @@ -4834,8 +4834,13 @@
> const MVT PtrVT, TLSModel::Model model) {
> DebugLoc dl = GA->getDebugLoc();
> // Get the Thread Pointer
> - SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
> - DebugLoc::getUnknownLoc(), PtrVT);
> + SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
> + DebugLoc::getUnknownLoc(), PtrVT,
> + DAG.getRegister(X86::GS, MVT::i32));
> +
> + SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
> + NULL, 0);
> +
> // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
> // exec)
> SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
> @@ -7149,7 +7154,7 @@
> case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
> case X86ISD::FRCP: return "X86ISD::FRCP";
> case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
> - case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
> + case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
> case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
> case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
> case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
> @@ -7473,7 +7478,7 @@
> unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
> MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
> // add 4 to displacement.
> - for (int i=0; i <= lastAddrIndx-1; ++i)
> + for (int i=0; i <= lastAddrIndx-2; ++i)
> (*MIB).addOperand(*argOpers[i]);
> MachineOperand newOp3 = *(argOpers[3]);
> if (newOp3.isImm())
> @@ -7481,6 +7486,7 @@
> else
> newOp3.setOffset(newOp3.getOffset()+4);
> (*MIB).addOperand(newOp3);
> + (*MIB).addOperand(*argOpers[lastAddrIndx]);
>
> // t3/4 are defined later, at the bottom of the loop
> unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Apr 7 16:37:46 2009
> @@ -188,8 +188,11 @@
> /// in order to obtain suitable precision.
> FRSQRT, FRCP,
>
> - // TLSADDR, THREAD_POINTER - Thread Local Storage.
> - TLSADDR, THREAD_POINTER,
> + // TLSADDR - Thread Local Storage.
> + TLSADDR,
> +
> + // SegmentBaseAddress - The address segment:0
> + SegmentBaseAddress,
>
> // EH_RETURN - Exception Handling helpers.
> EH_RETURN,
>
> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Apr 7 16:37:46 2009
> @@ -23,7 +23,7 @@
> def i64i8imm : Operand<i64>;
>
> def lea64mem : Operand<i64> {
> - let PrintMethod = "printi64mem";
> + let PrintMethod = "printlea64mem";
> let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Apr 7 16:37:46 2009
> @@ -66,6 +66,15 @@
> return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
> }
>
> +inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
> + int Offset) {
> + return MIB.addImm(1).addReg(0).addImm(Offset);
> +}
> +
> +inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
> + int Offset) {
> + return addLeaOffset(MIB, Offset).addReg(0);
> +}
>
> /// addRegOffset - This function is used to add a memory reference of the form
> /// [Reg + Offset], i.e., one with no scale or index, but with a
> @@ -74,8 +83,13 @@
> inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
> unsigned Reg, bool isKill,
> int Offset) {
> - return MIB.addReg(Reg, false, false, isKill)
> - .addImm(1).addReg(0).addImm(Offset);
> + return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
> +}
> +
> +inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
> + unsigned Reg, bool isKill,
> + int Offset) {
> + return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
> }
>
> /// addRegReg - This function is used to add a memory reference of the form:
> @@ -87,8 +101,8 @@
> .addReg(Reg2, false, false, isKill2).addImm(0);
> }
>
> -inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
> - const X86AddressMode &AM) {
> +inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
> + const X86AddressMode &AM) {
> assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
>
> if (AM.BaseType == X86AddressMode::RegBase)
> @@ -104,6 +118,11 @@
> return MIB.addImm(AM.Disp);
> }
>
> +inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
> + const X86AddressMode &AM) {
> + return addLeaAddress(MIB, AM).addReg(0);
> +}
> +
> /// addFrameReference - This function is used to add a reference to the base of
> /// an abstract object on the stack frame of the current function. This
> /// reference has base register as the FrameIndex offset until it is resolved.
> @@ -125,7 +144,7 @@
> MFI.getObjectOffset(FI) + Offset,
> MFI.getObjectSize(FI),
> MFI.getObjectAlignment(FI));
> - return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset)
> + return addOffset(MIB.addFrameIndex(FI), Offset)
> .addMemOperand(MMO);
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Apr 7 16:37:46 2009
> @@ -1138,9 +1138,9 @@
> assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
> unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
> : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
> - NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - .addReg(Dest, true, false, false, isDead),
> - Src, isKill, 1);
> + NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + .addReg(Dest, true, false, false, isDead),
> + Src, isKill, 1);
> break;
> }
> case X86::INC16r:
> @@ -1157,9 +1157,9 @@
> assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
> unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
> : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
> - NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - .addReg(Dest, true, false, false, isDead),
> - Src, isKill, -1);
> + NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + .addReg(Dest, true, false, false, isDead),
> + Src, isKill, -1);
> break;
> }
> case X86::DEC16r:
> @@ -1200,18 +1200,18 @@
> case X86::ADD64ri8:
> assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
> if (MI->getOperand(2).isImm())
> - NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
> - .addReg(Dest, true, false, false, isDead),
> - Src, isKill, MI->getOperand(2).getImm());
> + NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
> + .addReg(Dest, true, false, false, isDead),
> + Src, isKill, MI->getOperand(2).getImm());
> break;
> case X86::ADD32ri:
> case X86::ADD32ri8:
> assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
> if (MI->getOperand(2).isImm()) {
> unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
> - NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - .addReg(Dest, true, false, false, isDead),
> - Src, isKill, MI->getOperand(2).getImm());
> + NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
> + .addReg(Dest, true, false, false, isDead),
> + Src, isKill, MI->getOperand(2).getImm());
> }
> break;
> case X86::ADD16ri:
> @@ -1959,7 +1959,7 @@
> for (unsigned i = 0; i != NumAddrOps; ++i)
> MIB.addOperand(MOs[i]);
> if (NumAddrOps < 4) // FrameIndex only
> - MIB.addImm(1).addReg(0).addImm(0);
> + addOffset(MIB, 0);
>
> // Loop over the rest of the ri operands, converting them over.
> unsigned NumOps = MI->getDesc().getNumOperands()-2;
> @@ -1990,7 +1990,7 @@
> for (unsigned i = 0; i != NumAddrOps; ++i)
> MIB.addOperand(MOs[i]);
> if (NumAddrOps < 4) // FrameIndex only
> - MIB.addImm(1).addReg(0).addImm(0);
> + addOffset(MIB, 0);
> } else {
> MIB.addOperand(MO);
> }
> @@ -2008,7 +2008,7 @@
> for (unsigned i = 0; i != NumAddrOps; ++i)
> MIB.addOperand(MOs[i]);
> if (NumAddrOps < 4) // FrameIndex only
> - MIB.addImm(1).addReg(0).addImm(0);
> + addOffset(MIB, 0);
> return MIB.addImm(0);
> }
>
> @@ -2164,7 +2164,7 @@
> } else if (Ops.size() != 1)
> return NULL;
>
> - SmallVector<MachineOperand,4> MOs;
> + SmallVector<MachineOperand,X86AddrNumOperands> MOs;
> if (LoadMI->getOpcode() == X86::V_SET0 ||
> LoadMI->getOpcode() == X86::V_SETALLONES) {
> // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
> @@ -2193,6 +2193,7 @@
> MOs.push_back(MachineOperand::CreateImm(1));
> MOs.push_back(MachineOperand::CreateReg(0, false));
> MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
> + MOs.push_back(MachineOperand::CreateReg(0, false));
> } else {
> // Folding a normal load. Just copy the load's address operands.
> unsigned NumOps = LoadMI->getDesc().getNumOperands();
> @@ -2882,11 +2883,6 @@
> FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
> break;
> }
> - case X86::TLS_tp:
> - case X86::TLS_gs_ri:
> - FinalSize += 2;
> - FinalSize += sizeGlobalAddress(false);
> - break;
> }
> CurOp = NumOps;
> break;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Apr 7 16:37:46 2009
> @@ -243,7 +243,7 @@
> };
> }
>
> -const int X86AddrNumOperands = 4;
> +const int X86AddrNumOperands = 5;
>
> inline static bool isScale(const MachineOperand &MO) {
> return MO.isImm() &&
> @@ -251,7 +251,7 @@
> MO.getImm() == 4 || MO.getImm() == 8);
> }
>
> -inline static bool isMem(const MachineInstr *MI, unsigned Op) {
> +inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
> if (MI->getOperand(Op).isFI()) return true;
> return Op+4 <= MI->getNumOperands() &&
> MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
> @@ -262,6 +262,13 @@
> MI->getOperand(Op+3).isJTI());
> }
>
> +inline static bool isMem(const MachineInstr *MI, unsigned Op) {
> + if (MI->getOperand(Op).isFI()) return true;
> + return Op+5 <= MI->getNumOperands() &&
> + MI->getOperand(Op+4).isReg() &&
> + isLeaMem(MI, Op);
> +}
> +
> class X86InstrInfo : public TargetInstrInfoImpl {
> X86TargetMachine &TM;
> const X86RegisterInfo RI;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr 7 16:37:46 2009
> @@ -65,7 +65,7 @@
>
> def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
>
> -def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
> +def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
>
> def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
>
> @@ -142,7 +142,8 @@
>
> def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
> [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
> -def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
> +def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
> + SDT_X86SegmentBaseAddress, []>;
>
> def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
> [SDNPHasChain]>;
> @@ -167,7 +168,7 @@
> //
> class X86MemOperand<string printMethod> : Operand<iPTR> {
> let PrintMethod = printMethod;
> - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> }
>
> def i8mem : X86MemOperand<"printi8mem">;
> @@ -181,7 +182,7 @@
> def f128mem : X86MemOperand<"printf128mem">;
>
> def lea32mem : Operand<i32> {
> - let PrintMethod = "printi32mem";
> + let PrintMethod = "printlea32mem";
> let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
> }
>
> @@ -207,7 +208,7 @@
> //
>
> // Define X86 specific addressing mode.
> -def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
> +def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
> def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
> [add, mul, shl, or, frameindex], []>;
>
> @@ -2922,101 +2923,11 @@
> // Thread Local Storage Instructions
> //
>
> -// FIXME: there is duplication with the non-TLS case.
> -// There is a suggestion on how to fix this at
> -// http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075212.html
> -
> let Uses = [EBX] in
> def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
> "leal\t${sym:mem}(,%ebx,1), $dst",
> [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
>
> -let AddedComplexity = 10 in
> -def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
> - "movl\t%gs:($src), $dst",
> - [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
> -
> -let AddedComplexity = 15 in
> -def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS16_gs_ri : I<0x8B, Pseudo, (outs GR16:$dst), (ins i32imm:$src),
> - "movw\t%gs:${src:mem}, $dst",
> - [(set GR16:$dst,
> - (load (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS8_gs_ri : I<0x8B, Pseudo, (outs GR8:$dst), (ins i32imm:$src),
> - "movb\t%gs:${src:mem}, $dst",
> - [(set GR8:$dst,
> - (load (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movzwl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (extloadi32i16
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_sext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movswl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (sextloadi32i16
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_zext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movzwl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (zextloadi32i16
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movzbl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (extloadi32i8
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_sext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movsbl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (sextloadi32i8
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -let AddedComplexity = 15 in
> -def TLS_zext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
> - "movzbl\t%gs:${src:mem}, $dst",
> - [(set GR32:$dst,
> - (zextloadi32i8
> - (add X86TLStp,
> - (X86Wrapper tglobaltlsaddr:$src))))]>,
> - SegGS;
> -
> -def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
> - "movl\t%gs:0, $dst",
> - [(set GR32:$dst, X86TLStp)]>, SegGS;
> -
> let AddedComplexity = 5 in
> def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "movl\t%gs:$src, $dst",
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr 7 16:37:46 2009
> @@ -76,18 +76,18 @@
> // These are 'extloads' from a scalar to the low element of a vector, zeroing
> // the top elements. These are used for the SSE 'ss' and 'sd' instruction
> // forms.
> -def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
> +def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
> [SDNPHasChain, SDNPMayLoad]>;
> -def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
> +def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
> [SDNPHasChain, SDNPMayLoad]>;
>
> def ssmem : Operand<v4f32> {
> let PrintMethod = "printf32mem";
> - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> }
> def sdmem : Operand<v2f64> {
> let PrintMethod = "printf64mem";
> - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
> + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
> }
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 7 16:37:46 2009
> @@ -971,8 +971,8 @@
> } else if (MFI->hasVarSizedObjects()) {
> if (CSSize) {
> unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
> - MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
> - FramePtr, false, -CSSize);
> + MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
> + FramePtr, false, -CSSize);
> MBB.insert(MBBI, MI);
> } else
> BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Apr 7 16:37:46 2009
> @@ -168,6 +168,14 @@
>
> // Status flags register
> def EFLAGS : Register<"flags">;
> +
> + // Segment registers
> + def CS : Register<"cs">;
> + def DS : Register<"ds">;
> + def SS : Register<"ss">;
> + def ES : Register<"es">;
> + def FS : Register<"fs">;
> + def GS : Register<"gs">;
> }
>
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls10.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls10.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls10.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls10.ll Tue Apr 7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl %gs:0, %eax} %t
> -; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl \$i at NTPOFF, %eax} %t
> +; RUN: grep {addl %gs:0, %eax} %t
>
> @i = external hidden thread_local global i32
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls2.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls2.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls2.ll Tue Apr 7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl %gs:0, %eax} %t
> -; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl \$i at NTPOFF, %eax} %t
> +; RUN: grep {addl %gs:0, %eax} %t
>
> @i = thread_local global i32 15
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls6.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls6.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls6.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls6.ll Tue Apr 7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl %gs:0, %eax} %t
> -; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl \$i at NTPOFF, %eax} %t
> +; RUN: grep {addl %gs:0, %eax} %t
>
> @i = internal thread_local global i32 15
>
>
> Modified: llvm/trunk/test/CodeGen/X86/tls8.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls8.ll?rev=68552&r1=68551&r2=68552&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tls8.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tls8.ll Tue Apr 7 16:37:46 2009
> @@ -1,6 +1,6 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
> -; RUN: grep {movl %gs:0, %eax} %t
> -; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
> +; RUN: grep {movl \$i at NTPOFF, %eax} %t
> +; RUN: grep {addl %gs:0, %eax} %t
>
> @i = hidden thread_local global i32 15
>
>
>
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