[llvm-commits] [llvm] r66922 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/tls13.ll test/CodeGen/X86/tls14.ll

[Rafael Espindola]

> Ok, thanks for explaining this. How about this approach:
>
> On GNU and any other target that supports it, lower using a
> SegmentAddress node.  On other targets, lower using a load
> from a SegmentAddress node.  Make address-mode matching
> recognize SegmentAddress nodes (with appropriate special-cases
> for LEA).

That part is easy :-)

> Then in the Select phase, define a special "def : Pat" that maps
> the SegmentAddress node to a load from the SegmentAddress node
> with a predicate to limit it to GNU and similar targets.
>
> Does this sound reasonable?

The problem is that a (SegmentAddress ADDR, GS) has to be lowered to

(+ (LOAD GS:0) ADDR)

I am not  sure how to do this in a .td file, so I implemented this in
X86ISelDAGToDAG.cpp.

The bigger problem is when ADDR is not a symbol. For example, in a
InitialExec model, lowering will produce

(SegmentAddr (LOAD  ADDR), GS)

If we are just computing the addresses, this has to be lowered to

(+ (LOAD GS:0) (LOAD ADDR))

We should then combine the + and the (LOAD ADDR).

I have implemented this all, but I don't like the result all that
much. The function X86DAGToDAGISel::SelectSegmentAddress in particular
looks very complicated. Will get
more so when I add X86_64 :-(

I think I will try the idea of always lowering to (load gs:0) + ADDR
and then implementing some instruction folding after Select. I assume
that is possible, right?

> Dan


Cheers,
-- 
Rafael Avila de Espindola

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Registered in Dublin, Ireland | Registration Number: 368047
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