[llvm-commits] [llvm] r68355 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Target/TargetSelectionDAG.td lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp utils/TableGen/DAGISelEmitter.cpp
Dan Gohman
gohman at apple.com
Thu Apr 2 17:25:26 PDT 2009
Author: djg
Date: Thu Apr 2 19:25:26 2009
New Revision: 68355
URL: http://llvm.org/viewvc/llvm-project?rev=68355&view=rev
Log:
Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=68355&r1=68354&r2=68355&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Apr 2 19:25:26 2009
@@ -327,18 +327,6 @@
/// elements 1 to N-1 of the N-element vector are undefined.
SCALAR_TO_VECTOR,
- // EXTRACT_SUBREG - This node is used to extract a sub-register value.
- // This node takes a superreg and a constant sub-register index as operands.
- // Note sub-register indices must be increasing. That is, if the
- // sub-register index of a 8-bit sub-register is N, then the index for a
- // 16-bit sub-register must be at least N+1.
- EXTRACT_SUBREG,
-
- // INSERT_SUBREG - This node is used to insert a sub-register value.
- // This node takes a superreg, a subreg value, and a constant sub-register
- // index as operands.
- INSERT_SUBREG,
-
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*N], then return the top part.
MULHU, MULHS,
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=68355&r1=68354&r2=68355&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Apr 2 19:25:26 2009
@@ -406,11 +406,6 @@
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
-def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
- SDTypeProfile<1, 2, []>>;
-def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
- SDTypeProfile<1, 3, []>>;
-
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.
def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=68355&r1=68354&r2=68355&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Apr 2 19:25:26 2009
@@ -1589,23 +1589,6 @@
AddLegalizedOperand(SDValue(Node, i), Tmp1);
}
return Tmp2;
- case ISD::EXTRACT_SUBREG: {
- Tmp1 = LegalizeOp(Node->getOperand(0));
- ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
- assert(idx && "Operand must be a constant");
- Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
- }
- break;
- case ISD::INSERT_SUBREG: {
- Tmp1 = LegalizeOp(Node->getOperand(0));
- Tmp2 = LegalizeOp(Node->getOperand(1));
- ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
- assert(idx && "Operand must be a constant");
- Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
- }
- break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=68355&r1=68354&r2=68355&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Apr 2 19:25:26 2009
@@ -5165,9 +5165,6 @@
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
- case ISD::EXTRACT_SUBREG: return "extract_subreg";
- case ISD::INSERT_SUBREG: return "insert_subreg";
-
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=68355&r1=68354&r2=68355&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Apr 2 19:25:26 2009
@@ -1967,25 +1967,6 @@
<< " MVT::Other, Tmp1, Tmp2, Chain);\n"
<< "}\n\n";
- OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n"
- << " SDValue N0 = N.getOperand(0);\n"
- << " SDValue N1 = N.getOperand(1);\n"
- << " unsigned C = cast<ConstantSDNode>(N1)->getZExtValue();\n"
- << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
- << " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EXTRACT_SUBREG,\n"
- << " N.getValueType(), N0, Tmp);\n"
- << "}\n\n";
-
- OS << "SDNode *Select_INSERT_SUBREG(const SDValue &N) {\n"
- << " SDValue N0 = N.getOperand(0);\n"
- << " SDValue N1 = N.getOperand(1);\n"
- << " SDValue N2 = N.getOperand(2);\n"
- << " unsigned C = cast<ConstantSDNode>(N2)->getZExtValue();\n"
- << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
- << " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::INSERT_SUBREG,\n"
- << " N.getValueType(), N0, N1, Tmp);\n"
- << "}\n\n";
-
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDValue N) {\n"
<< " MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT();\n"
@@ -2020,8 +2001,6 @@
<< " case ISD::DBG_LABEL: return Select_DBG_LABEL(N);\n"
<< " case ISD::EH_LABEL: return Select_EH_LABEL(N);\n"
<< " case ISD::DECLARE: return Select_DECLARE(N);\n"
- << " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
- << " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n"
<< " case ISD::UNDEF: return Select_UNDEF(N);\n";
// Loop over all of the case statements, emiting a call to each method we
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