[llvm-commits] [llvm] r68137 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/shift-i128.ll test/CodeGen/X86/shift-i256.ll
Bill Wendling
isanbard at gmail.com
Tue Mar 31 13:08:06 PDT 2009
Author: void
Date: Tue Mar 31 15:08:05 2009
New Revision: 68137
URL: http://llvm.org/viewvc/llvm-project?rev=68137&view=rev
Log:
--- Merging (from foreign repository) r68133 into '.':
U lib/Target/X86/X86ISelLowering.cpp
i128 shift libcalls are not available on x86.
--- Merging (from foreign repository) r68134 into '.':
A test/CodeGen/X86/shift-i128.ll
A test/CodeGen/X86/shift-i256.ll
U lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
U lib/CodeGen/SelectionDAG/LegalizeTypes.h
Fully general expansion of integer shift of any size.
Added:
llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i128.ll
llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i256.ll
Modified:
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=68137&r1=68136&r2=68137&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Mar 31 15:08:05 2009
@@ -1231,6 +1231,78 @@
return false;
}
+/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
+/// of any size.
+bool DAGTypeLegalizer::
+ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue Amt = N->getOperand(1);
+ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ MVT ShTy = Amt.getValueType();
+ unsigned NVTBits = NVT.getSizeInBits();
+ assert(isPowerOf2_32(NVTBits) &&
+ "Expanded integer type size not a power of two!");
+ DebugLoc dl = N->getDebugLoc();
+
+ // Get the incoming operand to be shifted.
+ SDValue InL, InH;
+ GetExpandedInteger(N->getOperand(0), InL, InH);
+
+ SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
+ SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
+ SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
+ Amt, NVBitsNode, ISD::SETULT);
+
+ SDValue Lo1, Hi1, Lo2, Hi2;
+ switch (N->getOpcode()) {
+ default: assert(0 && "Unknown shift");
+ case ISD::SHL:
+ // ShAmt < NVTBits
+ Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
+ Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
+
+ // ShAmt >= NVTBits
+ Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
+ Hi2 = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
+
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
+ Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
+ return true;
+ case ISD::SRL:
+ // ShAmt < NVTBits
+ Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
+ Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
+
+ // ShAmt >= NVTBits
+ Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
+ Lo2 = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
+
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
+ Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
+ return true;
+ case ISD::SRA:
+ // ShAmt < NVTBits
+ Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
+ DAG.getConstant(NVTBits-1, ShTy));
+ Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
+
+ // ShAmt >= NVTBits
+ Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
+ Lo2 = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
+
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
+ Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
+ return true;
+ }
+
+ return false;
+}
+
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
@@ -1792,10 +1864,15 @@
else if (VT == MVT::i128)
LC = RTLIB::SRA_I128;
}
- assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
+
+ if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
+ SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
+ SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
+ return;
+ }
- SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
- SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
+ if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
+ assert(0 && "Unsupported shift!");
}
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=68137&r1=68136&r2=68137&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Mar 31 15:08:05 2009
@@ -353,6 +353,7 @@
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDValue &Lo, SDValue &Hi);
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
+ bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
// Integer Operand Expansion.
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=68137&r1=68136&r2=68137&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Tue Mar 31 15:08:05 2009
@@ -816,6 +816,13 @@
setOperationAction(ISD::UMULO, MVT::i32, Custom);
setOperationAction(ISD::UMULO, MVT::i64, Custom);
+ if (!Subtarget->is64Bit()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, 0);
+ setLibcallName(RTLIB::SRL_I128, 0);
+ setLibcallName(RTLIB::SRA_I128, 0);
+ }
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
setTargetDAGCombine(ISD::BUILD_VECTOR);
Added: llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i128.ll?rev=68137&view=auto
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i128.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i128.ll Tue Mar 31 15:08:05 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86
+; RUN: llvm-as < %s | llc -march=x86-64
+
+define void @t(i128 %x, i128 %a, i128* nocapture %r) nounwind {
+entry:
+ %0 = lshr i128 %x, %a
+ store i128 %0, i128* %r, align 16
+ ret void
+}
Added: llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i256.ll?rev=68137&view=auto
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i256.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/shift-i256.ll Tue Mar 31 15:08:05 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86
+; RUN: llvm-as < %s | llc -march=x86-64
+
+define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
+entry:
+ %0 = ashr i256 %x, %a
+ store i256 %0, i256* %r
+ ret void
+}
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