[llvm-commits] [llvm] r68092 - in /llvm/trunk: include/llvm/CodeGen/MachineBasicBlock.h lib/CodeGen/Spiller.cpp lib/CodeGen/Spiller.h lib/CodeGen/VirtRegMap.cpp lib/CodeGen/VirtRegMap.h lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
Bill Wendling
isanbard at gmail.com
Tue Mar 31 01:26:28 PDT 2009
Author: void
Date: Tue Mar 31 03:26:26 2009
New Revision: 68092
URL: http://llvm.org/viewvc/llvm-project?rev=68092&view=rev
Log:
Revert r68073. It's causing a failure in the Apple-style builds.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
llvm/trunk/lib/CodeGen/Spiller.cpp
llvm/trunk/lib/CodeGen/Spiller.h
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.h
llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Mar 31 03:26:26 2009
@@ -253,15 +253,6 @@
/// it returns end()
iterator getFirstTerminator();
- /// isOnlyReachableViaFallthough - Return true if this basic block has
- /// exactly one predecessor and the control transfer mechanism between
- /// the predecessor and this block is a fall-through.
- bool isOnlyReachableByFallthrough() const {
- return !pred_empty() &&
- next(pred_begin()) == pred_end() &&
- (*pred_begin())->getFirstTerminator() == (*pred_begin())->end();
- }
-
void pop_front() { Insts.pop_front(); }
void pop_back() { Insts.pop_back(); }
void push_back(MachineInstr *MI) { Insts.push_back(MI); }
Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Tue Mar 31 03:26:26 2009
@@ -578,6 +578,20 @@
DOUT << "**** Post Machine Instrs ****\n";
DEBUG(MF.dump());
+ // See if any of the spills we added are actually dead and can be deleted.
+ for (std::vector<MachineInstr*> >::iterator
+ I = AddedSpills.begin(), E = AddedSpills.end(); I != E; ++I) {
+ MachineInstr *MI = *I;
+
+ if (VRM.OnlyUseOfStackSlot(MI)) {
+ MachineBasicBlock *MBB = MI->getParent();
+ DOUT << "Removed dead store:\t" << *MI;
+ VRM.RemoveMachineInstrFromMaps(MI);
+ MBB->erase(MI);
+ ++NumDSE;
+ }
+ }
+
// Mark unused spill slots.
MachineFrameInfo *MFI = MF.getFrameInfo();
int SS = VRM.getLowSpillSlot();
@@ -588,6 +602,7 @@
++NumDSS;
}
+ AddedSpills.clear();
return true;
}
@@ -798,9 +813,50 @@
return false;
}
+void LocalSpiller::RemoveDeadStore(MachineInstr *Store,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator &MII,
+ SmallSet<MachineInstr*, 4> &ReMatDefs,
+ BitVector &RegKills,
+ std::vector<MachineOperand*> &KillOps,
+ VirtRegMap &VRM) {
+ // If there is a dead store to this stack slot, nuke it now.
+ DOUT << "Removed dead store:\t" << *Store;
+ ++NumDSE;
+ SmallVector<unsigned, 2> KillRegs;
+ InvalidateKills(*Store, RegKills, KillOps, &KillRegs);
+
+ MachineBasicBlock::iterator PrevMII = Store;
+ bool CheckDef = PrevMII != MBB.begin();
+ if (CheckDef) --PrevMII;
+
+ VRM.RemoveMachineInstrFromMaps(Store);
+ MBB.erase(Store);
+
+ if (CheckDef) {
+ // Look at defs of killed registers on the store. Mark the defs as dead
+ // since the store has been deleted and they aren't being reused.
+ for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
+ bool HasOtherDef = false;
+
+ if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
+ MachineInstr *DeadDef = PrevMII;
+
+ if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
+ // FIXME: This assumes a remat def does not have side effects.
+ VRM.RemoveMachineInstrFromMaps(DeadDef);
+ MBB.erase(DeadDef);
+ ++NumDRM;
+ }
+ }
+ }
+ }
+}
+
/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
/// the last store to the same slot is now dead. If so, remove the last store.
-void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
+void
+LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MII,
int Idx, unsigned PhysReg, int StackSlot,
const TargetRegisterClass *RC,
@@ -816,36 +872,8 @@
DOUT << "Store:\t" << *StoreMI;
// If there is a dead store to this stack slot, nuke it now.
- if (LastStore) {
- DOUT << "Removed dead store:\t" << *LastStore;
- ++NumDSE;
- SmallVector<unsigned, 2> KillRegs;
- InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
- MachineBasicBlock::iterator PrevMII = LastStore;
- bool CheckDef = PrevMII != MBB.begin();
- if (CheckDef)
- --PrevMII;
- VRM.RemoveMachineInstrFromMaps(LastStore);
- MBB.erase(LastStore);
- if (CheckDef) {
- // Look at defs of killed registers on the store. Mark the defs
- // as dead since the store has been deleted and they aren't
- // being reused.
- for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
- bool HasOtherDef = false;
- if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
- MachineInstr *DeadDef = PrevMII;
- if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
- // FIXME: This assumes a remat def does not have side
- // effects.
- VRM.RemoveMachineInstrFromMaps(DeadDef);
- MBB.erase(DeadDef);
- ++NumDRM;
- }
- }
- }
- }
- }
+ if (LastStore)
+ RemoveDeadStore(LastStore, MBB, MII, ReMatDefs, RegKills, KillOps, VRM);
LastStore = next(MII);
@@ -1060,6 +1088,7 @@
if (VRM.isSpillPt(&MI)) {
std::vector<std::pair<unsigned,bool> > &SpillRegs =
VRM.getSpillPtSpills(&MI);
+
for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
unsigned VirtReg = SpillRegs[i].first;
bool isKill = SpillRegs[i].second;
@@ -1073,7 +1102,9 @@
VRM.addSpillSlotUse(StackSlot, StoreMI);
DOUT << "Store:\t" << *StoreMI;
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
+ AddedSpills.push_back(StoreMI);
}
+
NextMII = next(MII);
}
Modified: llvm/trunk/lib/CodeGen/Spiller.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.h (original)
+++ llvm/trunk/lib/CodeGen/Spiller.h Tue Mar 31 03:26:26 2009
@@ -285,6 +285,7 @@
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
DenseMap<MachineInstr*, unsigned> DistanceMap;
+ std::vector<MachineInstr*> AddedSpills;
public:
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM);
private:
@@ -305,6 +306,14 @@
std::vector<MachineOperand*> &KillOps,
const TargetRegisterInfo *TRI,
VirtRegMap &VRM);
+ void RemoveDeadStore(MachineInstr *Store,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator &MII,
+ SmallSet<MachineInstr*, 4> &ReMatDefs,
+ BitVector &RegKills,
+ std::vector<MachineOperand*> &KillOps,
+ VirtRegMap &VRM);
+
void SpillRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MII,
int Idx, unsigned PhysReg, int StackSlot,
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Mar 31 03:26:26 2009
@@ -188,7 +188,7 @@
if (MF->getFrameInfo()->isFixedObjectIndex(FI))
continue;
// This stack reference was produced by instruction selection and
- // is not a spill
+ // is not a spill.
if (FI < LowSpillSlot)
continue;
assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
@@ -201,6 +201,27 @@
EmergencySpillMap.erase(MI);
}
+bool VirtRegMap::OnlyUseOfStackSlot(const MachineInstr *MI) const {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isFI())
+ continue;
+ int FI = MO.getIndex();
+ if (MF->getFrameInfo()->isFixedObjectIndex(FI))
+ continue;
+ // This stack reference was produced by instruction selection and
+ // is not a spill.
+ if (FI < LowSpillSlot)
+ continue;
+ assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
+ && "Invalid spill slot");
+ if (SpillSlotToUsesMap[FI - LowSpillSlot].size() != 1)
+ return false;
+ }
+
+ return true;
+}
+
void VirtRegMap::print(std::ostream &OS, const Module* M) const {
const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.h?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.h (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.h Tue Mar 31 03:26:26 2009
@@ -430,6 +430,8 @@
/// the folded instruction map and spill point map.
void RemoveMachineInstrFromMaps(MachineInstr *MI);
+ bool OnlyUseOfStackSlot(const MachineInstr *MI) const;
+
void print(std::ostream &OS, const Module* M = 0) const;
void print(std::ostream *OS) const { if (OS) print(*OS); }
void dump() const;
Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=68092&r1=68091&r2=68092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Mar 31 03:26:26 2009
@@ -238,12 +238,7 @@
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
- if (!VerboseAsm && (I->pred_empty() || I->isOnlyReachableByFallthrough())) {
- // This is an entry block or a block that's only reachable via a
- // fallthrough edge. In non-VerboseAsm mode, don't print the label.
- assert((I->pred_empty() || (*I->pred_begin())->isLayoutSuccessor(I)) &&
- "Fall-through predecessor not adjacent to its successor!");
- } else {
+ if (!I->pred_empty()) {
printBasicBlockLabel(I, true, true, VerboseAsm);
O << '\n';
}
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