[llvm-commits] [llvm] r67742 - in /llvm/trunk/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp

[Bill Wendling]

Author: void
Date: Thu Mar 26 01:14:09 2009
New Revision: 67742

URL: http://llvm.org/viewvc/llvm-project?rev=67742&view=rev
Log:
Pull transform from target-dependent code into target-independent code.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=67742&r1=67741&r2=67742&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 26 01:14:09 2009
@@ -4355,6 +4355,55 @@
                        N1.getOperand(0), N1.getOperand(1), N2);
   }
 
+  if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
+    // Match this pattern so that we can generate simpler code:
+    //
+    //   %a = ...
+    //   %b = and i32 %a, 2
+    //   %c = srl i32 %b, 1
+    //   brcond i32 %c ...
+    //
+    // into
+    // 
+    //   %a = ...
+    //   %b = and %a, 2
+    //   %c = setcc eq %b, 0
+    //   brcond %c ...
+    //
+    // This applies only when the AND constant value has one bit set and the
+    // SRL constant is equal to the log2 of the AND constant. The back-end is
+    // smart enough to convert the result into a TEST/JMP sequence.
+    SDValue Op0 = N1.getOperand(0);
+    SDValue Op1 = N1.getOperand(1);
+
+    if (Op0.getOpcode() == ISD::AND &&
+        Op0.hasOneUse() &&
+        Op1.getOpcode() == ISD::Constant) {
+      SDValue AndOp0 = Op0.getOperand(0);
+      SDValue AndOp1 = Op0.getOperand(1);
+
+      if (AndOp1.getOpcode() == ISD::Constant) {
+        const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
+
+        if (AndConst.isPowerOf2() &&
+            cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
+          SDValue SetCC =
+            DAG.getSetCC(N->getDebugLoc(),
+                         TLI.getSetCCResultType(Op0.getValueType()),
+                         Op0, DAG.getConstant(0, Op0.getValueType()),
+                         ISD::SETNE);
+
+          // Replace the uses of SRL with SETCC
+          DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
+          removeFromWorkList(N1.getNode());
+          DAG.DeleteNode(N1.getNode());
+          return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
+                             MVT::Other, Chain, SetCC, N2);
+        }
+      }
+    }
+  }
+
   return SDValue();
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=67742&r1=67741&r2=67742&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Mar 26 01:14:09 2009
@@ -5870,45 +5870,6 @@
       CC = DAG.getConstant(CCode, MVT::i8);
       Cond = Cond.getOperand(0).getOperand(1);
       addTest = false;
-    } else if (Cond.hasOneUse() && Cond.getOpcode() == ISD::SRL) {
-      // Match this pattern so that we can generate simpler code:
-      //
-      //   %a = ...
-      //   %b = and i32 %a, 2
-      //   %c = srl i32 %b, 1
-      //   %d = br i32 %c, 
-      //
-      // into
-      // 
-      //   %a = ...
-      //   %b = and %a, 2
-      //   %c = X86ISD::CMP %b, 0
-      //   %d = X86ISD::BRCOND %c ...
-      //
-      // This applies only when the AND constant value has one bit set and the
-      // SRL constant is equal to the log2 of the AND constant. The back-end is
-      // smart enough to convert the result into a TEST/JMP sequence.
-      SDValue Op0 = Cond.getOperand(0);
-      SDValue Op1 = Cond.getOperand(1);
-
-      if (Op0.getOpcode() == ISD::AND &&
-          Op0.hasOneUse() &&
-          Op1.getOpcode() == ISD::Constant) {
-        SDValue AndOp0 = Op0.getOperand(0);
-        SDValue AndOp1 = Op0.getOperand(1);
-
-        if (AndOp1.getOpcode() == ISD::Constant) {
-          const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
-
-          if (AndConst.isPowerOf2() &&
-              cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
-            CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-            Cond = EmitTest(Op0, X86::COND_NE, DAG);
-            return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
-                               Chain, Dest, CC, Cond);
-          }
-        }
-      }
     }
   }