[llvm-commits] [llvm] r67547 - in /llvm/branches/Apple/Dib: lib/CodeGen/LowerSubregs.cpp test/CodeGen/X86/subreg-to-reg-2.ll

[Bill Wendling]

Author: void
Date: Mon Mar 23 13:37:24 2009
New Revision: 67547

URL: http://llvm.org/viewvc/llvm-project?rev=67547&view=rev
Log:
--- Merging (from foreign repository) r67511 into '.':
A    test/CodeGen/X86/subreg-to-reg-2.ll
U    lib/CodeGen/LowerSubregs.cpp

Do not fold away subreg_to_reg if the source register has a sub-register
index. That means the source register is taking a sub-register of a larger
register. e.g. On x86

%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3

The first def is defining RAX, not EAX so the top bits were not zero-extended.

Added:
    llvm/branches/Apple/Dib/test/CodeGen/X86/subreg-to-reg-2.ll
Modified:
    llvm/branches/Apple/Dib/lib/CodeGen/LowerSubregs.cpp

Modified: llvm/branches/Apple/Dib/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/LowerSubregs.cpp?rev=67547&r1=67546&r2=67547&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/LowerSubregs.cpp Mon Mar 23 13:37:24 2009
@@ -165,11 +165,12 @@
           
   unsigned DstReg  = MI->getOperand(0).getReg();
   unsigned InsReg  = MI->getOperand(2).getReg();
-  unsigned SubIdx  = MI->getOperand(3).getImm();     
+  unsigned InsSIdx = MI->getOperand(2).getSubReg();
+  unsigned SubIdx  = MI->getOperand(3).getImm();
 
   assert(SubIdx != 0 && "Invalid index for insert_subreg");
   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
-  
+
   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
          "Insert destination must be in a physical register");
   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
@@ -177,8 +178,13 @@
 
   DOUT << "subreg: CONVERTING: " << *MI;
 
-  if (DstSubReg == InsReg) {
+  if (DstSubReg == InsReg && InsSIdx == 0) {
     // No need to insert an identify copy instruction.
+    // Watch out for case like this:
+    // %RAX<def> = ...
+    // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
+    // The first def is defining RAX, not EAX so the top bits were not
+    // zero extended.
     DOUT << "subreg: eliminated!";
   } else {
     // Insert sub-register copy

Added: llvm/branches/Apple/Dib/test/CodeGen/X86/subreg-to-reg-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/subreg-to-reg-2.ll?rev=67547&view=auto

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/subreg-to-reg-2.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/subreg-to-reg-2.ll Mon Mar 23 13:37:24 2009
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl
+; rdar://6707985
+
+	%XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" }
+	%XXValue = type opaque
+	%"struct.XXC::ArrayStorage" = type { i32, i32, i32, i8*, i8*, [1 x %XXValue*] }
+	%"struct.XXC::XXArray" = type { %XXOO, i32, %"struct.XXC::ArrayStorage"* }
+	%"struct.XXC::XXCC" = type { i32 (...)**, i8* }
+	%"struct.XXC::XXOO::$_71" = type { [2 x %XXValue*] }
+
+define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind {
+prologue:
+	%array = load %XXValue** inttoptr (i64 11111111 to %XXValue**)		; <%XXValue*> [#uses=0]
+	%index = load %XXValue** inttoptr (i64 22222222 to %XXValue**)		; <%XXValue*> [#uses=1]
+	%tmp = ptrtoint %XXValue* %index to i64		; <i64> [#uses=2]
+	store i64 %tmp, i64* %out
+	%tmp6 = trunc i64 %tmp to i32		; <i32> [#uses=1]
+	br label %bb5
+
+bb5:		; preds = %prologue
+	%tmp10 = zext i32 %tmp6 to i64		; <i64> [#uses=1]
+	%tmp11 = getelementptr %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10		; <%XXValue**> [#uses=1]
+	%tmp12 = load %XXValue** %tmp11, align 8		; <%XXValue*> [#uses=1]
+	ret %XXValue* %tmp12
+}