[llvm-commits] register subclass patch!

[Bruno Cardoso Lopes]

Hi all,

Mips has two register classes for f32:

def FGR32 : RegisterClass<"Mips", [f32], 32,
  [F0, F1, F2, F3, F12, F13, F14, F15,
   F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
   F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>

def AFGR32 : RegisterClass<"Mips", [f32], 32,
  [F0, F2, F12, F14,
  F4, F6, F8, F10, F16, F18,
  F20, F22, F24, F26, F28, F30,
  F31]>

Tblgen will set AFGR32 as a subclass of FGR32, which it's a not
desired behavior in Mips because only one of them is added in
TargetLowering for each execution (it relies on the ABI and other
attrs). So, if assignments for both classes at the same program
shouldn't be made, I attached a simple patch to avoid the subclass
attribution when desired by the target (this is causing some troubles
for Mips O32 calling convention). Does anyone suggest another
approach?

I see this is somehow related to the thread
http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-March/020948.html
But it seems that the solutions provided in this thread doesn't solve
this specific problem in a explicit way.

Cheers,

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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