[llvm-commits] [llvm] r67044 - in /llvm/branches/Apple/Dib: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-i1.ll test/CodeGen/X86/fast-isel-phys.ll test/CodeGen/X86/fast-isel-trunc.ll test/CodeGen/X86/fast-isel.ll
Bill Wendling
isanbard at gmail.com
Mon Mar 16 11:08:54 PDT 2009
Author: void
Date: Mon Mar 16 13:08:53 2009
New Revision: 67044
URL: http://llvm.org/viewvc/llvm-project?rev=67044&view=rev
Log:
--- Merging (from foreign repository) r66941 into '.':
A test/CodeGen/X86/fast-isel-i1.ll
U include/llvm/CodeGen/FastISel.h
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/Target/X86/X86FastISel.cpp
--- Merging (from foreign repository) r66988 into '.':
U test/CodeGen/X86/fast-isel-phys.ll
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-trunc.ll
G lib/CodeGen/SelectionDAG/FastISel.cpp
G lib/Target/X86/X86FastISel.cpp
Added:
llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-i1.ll
Modified:
llvm/branches/Apple/Dib/include/llvm/CodeGen/FastISel.h
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-phys.ll
llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-trunc.ll
llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel.ll
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/FastISel.h?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/FastISel.h Mon Mar 16 13:08:53 2009
@@ -269,6 +269,11 @@
unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx);
+ /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
+ /// with all but the least significant bit set to zero.
+ unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
+ unsigned Op);
+
/// FastEmitBranch - Emit an unconditional branch to the given block,
/// unless it is the immediate (fall-through) successor, and update
/// the CFG.
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Mar 16 13:08:53 2009
@@ -477,27 +477,42 @@
MVT DstVT = TLI.getValueType(I->getType());
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(DstVT))
+ DstVT == MVT::Other || !DstVT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
+ // Check if the destination type is legal. Or as a special case,
+ // it may be i1 if we're doing a truncate because that's
+ // easy and somewhat common.
+ if (!TLI.isTypeLegal(DstVT))
+ if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
+ // Unhandled type. Halt "fast" selection and bail.
+ return false;
+
// Check if the source operand is legal. Or as a special case,
// it may be i1 if we're doing zero-extension because that's
- // trivially easy and somewhat common.
- if (!TLI.isTypeLegal(SrcVT)) {
- if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
- SrcVT = TLI.getTypeToTransformTo(SrcVT);
- else
+ // easy and somewhat common.
+ if (!TLI.isTypeLegal(SrcVT))
+ if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
// Unhandled type. Halt "fast" selection and bail.
return false;
- }
-
+
unsigned InputReg = getRegForValue(I->getOperand(0));
if (!InputReg)
// Unhandled operand. Halt "fast" selection and bail.
return false;
-
+
+ // If the operand is i1, arrange for the high bits in the register to be zero.
+ if (SrcVT == MVT::i1) {
+ SrcVT = TLI.getTypeToTransformTo(SrcVT);
+ InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
+ if (!InputReg)
+ return false;
+ }
+ // If the result is i1, truncate to the target's type for i1 first.
+ if (DstVT == MVT::i1)
+ DstVT = TLI.getTypeToTransformTo(DstVT);
+
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
DstVT.getSimpleVT(),
Opcode,
@@ -970,3 +985,9 @@
}
return ResultReg;
}
+
+/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
+/// with all but the least significant bit set to zero.
+unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
+ return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
+}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp Mon Mar 16 13:08:53 2009
@@ -662,12 +662,14 @@
}
bool X86FastISel::X86SelectZExt(Instruction *I) {
- // Special-case hack: The only i1 values we know how to produce currently
- // set the upper bits of an i8 value to zero.
+ // Handle zero-extension from i1 to i8, which is common.
if (I->getType() == Type::Int8Ty &&
I->getOperand(0)->getType() == Type::Int1Ty) {
unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
+ // Set the high bits to zero.
+ ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
+ if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg);
return true;
}
@@ -1402,6 +1404,19 @@
return X86SelectFPTrunc(I);
case Instruction::ExtractValue:
return X86SelectExtractValue(I);
+ case Instruction::IntToPtr: // Deliberate fall-through.
+ case Instruction::PtrToInt: {
+ MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ MVT DstVT = TLI.getValueType(I->getType());
+ if (DstVT.bitsGT(SrcVT))
+ return X86SelectZExt(I);
+ if (DstVT.bitsLT(SrcVT))
+ return X86SelectTrunc(I);
+ unsigned Reg = getRegForValue(I->getOperand(0));
+ if (Reg == 0) return false;
+ UpdateValueMap(I, Reg);
+ return true;
+ }
}
return false;
Added: llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-i1.ll?rev=67044&view=auto
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-i1.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-i1.ll Mon Mar 16 13:08:53 2009
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=x86 -fast-isel | grep {andb \$1, %}
+
+declare i64 @bar(i64)
+
+define i32 @foo(i64 %x) nounwind {
+ %y = add i64 %x, -3 ; <i64> [#uses=1]
+ %t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
+ %s = mul i64 %t, 77 ; <i64> [#uses=1]
+ %z = trunc i64 %s to i1 ; <i1> [#uses=1]
+ br label %next
+
+next: ; preds = %0
+ %u = zext i1 %z to i32 ; <i32> [#uses=1]
+ %v = add i32 %u, 1999 ; <i32> [#uses=1]
+ br label %exit
+
+exit: ; preds = %next
+ ret i32 %v
+}
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-phys.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-phys.ll?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-phys.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-phys.ll Mon Mar 16 13:08:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86
+; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86
define i8 @t2(i8 %a, i8 %c) nounwind {
%tmp = shl i8 %a, %c
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-trunc.ll?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-trunc.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel-trunc.ll Mon Mar 16 13:08:53 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast-isel
-; RUN: llvm-as < %s | llc -march=x86-64 -fast-isel
+; RUN: llvm-as < %s | llc -march=x86 -fast-isel -fast-isel-abort
+; RUN: llvm-as < %s | llc -march=x86-64 -fast-isel -fast-isel-abort
define i8 @t1(i32 %x) signext nounwind {
%tmp1 = trunc i32 %x to i8
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel.ll?rev=67044&r1=67043&r2=67044&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/fast-isel.ll Mon Mar 16 13:08:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86 -mattr=sse2
+; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86 -mattr=sse2
; This tests very minimal fast-isel functionality.
@@ -47,3 +47,12 @@
%tmp2 = bitcast i32 0 to i32
ret i32 %tmp2
}
+
+define i1 @ptrtoint(i8* %p) nounwind {
+ %t = ptrtoint i8* %p to i1
+ ret i1 %t
+}
+define i8* @inttoptr(i1 %p) nounwind {
+ %t = inttoptr i1 %p to i8*
+ ret i8* %t
+}
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