[llvm-commits] [llvm] r66929 - /llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Fri Mar 13 12:20:48 PDT 2009
Author: void
Date: Fri Mar 13 14:20:48 2009
New Revision: 66929
URL: http://llvm.org/viewvc/llvm-project?rev=66929&view=rev
Log:
Unbreak build.
Modified:
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=66929&r1=66928&r2=66929&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Fri Mar 13 14:20:48 2009
@@ -8111,16 +8111,16 @@
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
- DebugLoc dl = N->getDebugLoc();
+ DebugLoc DL = N->getDebugLoc();
SDValue Cond = N->getOperand(0);
+ // Get the LHS/RHS of the select.
+ SDValue LHS = N->getOperand(1);
+ SDValue RHS = N->getOperand(2);
// If we have SSE[12] support, try to form min/max nodes.
if (Subtarget->hasSSE2() &&
(N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
if (Cond.getOpcode() == ISD::SETCC) {
- // Get the LHS/RHS of the select.
- SDValue LHS = N->getOperand(1);
- SDValue RHS = N->getOperand(2);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;
@@ -8173,7 +8173,7 @@
}
if (Opcode)
- return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS);
+ return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
}
}
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