[llvm-commits] Addition to SplitVectorOp

[Villmow, Micah]

Split vector op does not currently handle splitting vector based shift
operations.

@@ -7206,11 +7206,14 @@

     case ISD::AND:

     case ISD::OR:

     case ISD::XOR:

     case ISD::UREM:

     case ISD::SREM:

<    case ISD::FREM: {

->   case ISD::FREM:

->   case ISD::SHL:

->   case ISD::SRA:

->   case ISD::SRL:{

       SDValue LL, LH, RL, RH;

       SplitVectorOp(Node->getOperand(0), LL, LH);

       SplitVectorOp(Node->getOperand(1), RL, RH);

       

       Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);

 

 

The following code snippet adds in this support.

 

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

S1-609 One AMD Place

Sunnyvale, CA. 94085

P: 408-749-3966

 

 

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