[llvm-commits] [llvm] r66669 - /llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp

[Dan Gohman]

Author: djg
Date: Wed Mar 11 13:06:20 2009
New Revision: 66669

URL: http://llvm.org/viewvc/llvm-project?rev=66669&view=rev
Log:
Merge from trunk:

r63643 | djg | 2009-02-03 10:57:45 -0800 (Tue, 03 Feb 2009) | 5 lines

Change the post-RA scheduler to iterate through the
basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.


Modified:
    llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp

Modified: llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp?rev=66669&r1=66668&r2=66669&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp Wed Mar 11 13:06:20 2009
@@ -189,15 +189,17 @@
        MBB != MBBe; ++MBB) {
     // Schedule each sequence of instructions not interrupted by a label
     // or anything else that effectively needs to shut down scheduling.
-    MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
-    for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
+    MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
+    for (MachineBasicBlock::iterator I = Current; I != Top; ) {
+      MachineInstr *MI = --I;
       if (MI->getDesc().isTerminator() || MI->isLabel()) {
-        Scheduler.Run(0, MBB, Current, MI);
+        Scheduler.Run(0, MBB, next(I), Current);
         Scheduler.EmitSchedule();
-        Current = next(MI);
+        Current = I;
       }
+    }
 
-    Scheduler.Run(0, MBB, Current, End);
+    Scheduler.Run(0, MBB, Top, Current);
     Scheduler.EmitSchedule();
   }
 
@@ -414,10 +416,10 @@
   // instructions from the bottom up, tracking information about liveness
   // as we go to help determine which registers are available.
   bool Changed = false;
-  unsigned Count = BB->size() - 1;
-  for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
-       I != E; ++I, --Count) {
-    MachineInstr *MI = &*I;
+  unsigned Count = SUnits.size() - 1;
+  for (MachineBasicBlock::iterator I = End, E = Begin;
+       I != E; --Count) {
+    MachineInstr *MI = --I;
 
     // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
     // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF