[llvm-commits] [llvm] r65516 - in /llvm/branches/Apple/Dib: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2009-02-25-CommuteBug.ll

[Bill Wendling]

Author: void
Date: Thu Feb 26 01:38:09 2009
New Revision: 65516

URL: http://llvm.org/viewvc/llvm-project?rev=65516&view=rev
Log:
Pull r65499 into Dib:

ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these
intrinsics expect the high bits will not be modified.

Added:
    llvm/branches/Apple/Dib/test/CodeGen/X86/2009-02-25-CommuteBug.ll
      - copied unchanged from r65499, llvm/trunk/test/CodeGen/X86/2009-02-25-CommuteBug.ll
Modified:
    llvm/branches/Apple/Dib/include/llvm/IntrinsicsX86.td
    llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td

Modified: llvm/branches/Apple/Dib/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/IntrinsicsX86.td?rev=65516&r1=65515&r2=65516&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/IntrinsicsX86.td (original)
+++ llvm/branches/Apple/Dib/include/llvm/IntrinsicsX86.td Thu Feb 26 01:38:09 2009
@@ -19,13 +19,13 @@
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
               Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
-                         llvm_v4f32_ty], [IntrNoMem, Commutative]>;
+                         llvm_v4f32_ty], [IntrNoMem]>;
   def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
               Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
                          llvm_v4f32_ty], [IntrNoMem]>;
   def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
               Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
-                         llvm_v4f32_ty], [IntrNoMem, Commutative]>;
+                         llvm_v4f32_ty], [IntrNoMem]>;
   def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
               Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
                          llvm_v4f32_ty], [IntrNoMem]>;
@@ -176,13 +176,13 @@
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">,
               Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
-                         llvm_v2f64_ty], [IntrNoMem, Commutative]>;
+                         llvm_v2f64_ty], [IntrNoMem]>;
   def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">,
               Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
                          llvm_v2f64_ty], [IntrNoMem]>;
   def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">,
               Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
-                         llvm_v2f64_ty], [IntrNoMem, Commutative]>;
+                         llvm_v2f64_ty], [IntrNoMem]>;
   def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">,
               Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
                          llvm_v2f64_ty], [IntrNoMem]>;

Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td?rev=65516&r1=65515&r2=65516&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td Thu Feb 26 01:38:09 2009
@@ -523,7 +523,7 @@
 /// In addition, we also have a special variant of the scalar form here to
 /// represent the associated intrinsic operation.  This form is unlike the
 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
-/// and leaves the top elements undefined.
+/// and leaves the top elements unmodified (therefore these cannot be commuted).
 ///
 /// These three forms can each be reg+reg or reg+mem, so there are a total of
 /// six "instructions".
@@ -563,9 +563,7 @@
   def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
                                      (ins VR128:$src1, VR128:$src2),
                      !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
-    let isCommutable = Commutable;
-  }
+                     [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
 
   // Intrinsic operation, reg+mem.
   def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
@@ -1272,7 +1270,7 @@
 /// In addition, we also have a special variant of the scalar form here to
 /// represent the associated intrinsic operation.  This form is unlike the
 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
-/// and leaves the top elements undefined.
+/// and leaves the top elements unmodified (therefore these cannot be commuted).
 ///
 /// These three forms can each be reg+reg or reg+mem, so there are a total of
 /// six "instructions".
@@ -1312,9 +1310,7 @@
   def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
                                      (ins VR128:$src1, VR128:$src2),
                      !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
-    let isCommutable = Commutable;
-  }
+                     [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
 
   // Intrinsic operation, reg+mem.
   def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),