[llvm-commits] [llvm] r65351 - in /llvm/branches/Apple/Dib: lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrMMX.td test/CodeGen/X86/ret-mmx.ll
Bill Wendling
isanbard at gmail.com
Mon Feb 23 15:58:39 PST 2009
Author: void
Date: Mon Feb 23 17:58:39 2009
New Revision: 65351
URL: http://llvm.org/viewvc/llvm-project?rev=65351&view=rev
Log:
--- Merging (from foreign repository) r65313 into '.':
U test/CodeGen/X86/ret-mmx.ll
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CallingConv.td
U lib/Target/X86/X86InstrMMX.td
Only v1i16 (i.e. _m64) is returned via RAX / RDX.
Modified:
llvm/branches/Apple/Dib/lib/Target/X86/X86CallingConv.td
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrMMX.td
llvm/branches/Apple/Dib/test/CodeGen/X86/ret-mmx.ll
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86CallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86CallingConv.td?rev=65351&r1=65350&r2=65351&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86CallingConv.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86CallingConv.td Mon Feb 23 17:58:39 2009
@@ -72,9 +72,11 @@
CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
- // MMX vector types are always returned in RAX. This seems to disagree with
- // ABI documentation but is bug compatible with gcc.
- CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[RAX]>>,
+ // MMX vector types are always returned in XMM0 except for v1i64 which is
+ // returned in RAX. This disagrees with ABI documentation but is bug
+ // compatible with gcc.
+ CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
+ CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
CCDelegateTo<RetCC_X86Common>
]>;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=65351&r1=65350&r2=65351&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Mon Feb 23 17:58:39 2009
@@ -589,8 +589,6 @@
addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
- // FIXME: add MMX packed arithmetics
-
setOperationAction(ISD::ADD, MVT::v8i8, Legal);
setOperationAction(ISD::ADD, MVT::v4i16, Legal);
setOperationAction(ISD::ADD, MVT::v2i32, Legal);
@@ -997,12 +995,15 @@
continue;
}
- // 64-bit vector (MMX) values are returned in RAX.
+ // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
+ // which is returned in RAX / RDX.
if (Subtarget->is64Bit()) {
MVT ValVT = ValToCopy.getValueType();
- if (VA.getLocReg() == X86::RAX &&
- ValVT.isVector() && ValVT.getSizeInBits() == 64)
+ if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
+ if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
+ ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
+ }
}
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
@@ -1081,10 +1082,18 @@
SDValue Val;
if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
- // For x86-64, MMX values are returned in RAX.
- Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
- MVT::i64, InFlag).getValue(1);
- Val = Chain.getValue(0);
+ // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
+ if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
+ Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
+ MVT::v2i64, InFlag).getValue(1);
+ Val = Chain.getValue(0);
+ Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
+ Val, DAG.getConstant(0, MVT::i64));
+ } else {
+ Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
+ MVT::i64, InFlag).getValue(1);
+ Val = Chain.getValue(0);
+ }
Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
} else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
@@ -6627,7 +6636,7 @@
DebugLoc dl = Node->getDebugLoc();
MVT T = Node->getValueType(0);
SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
- DAG.getConstant(0, T), Node->getOperand(2));
+ DAG.getConstant(0, T), Node->getOperand(2));
return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
cast<AtomicSDNode>(Node)->getMemoryVT(),
Node->getOperand(0),
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrMMX.td?rev=65351&r1=65350&r2=65351&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrMMX.td Mon Feb 23 17:58:39 2009
@@ -156,10 +156,12 @@
let neverHasSideEffects = 1 in
def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
- "movd\t{$src, $dst|$dst, $src}", []>;
+ "movd\t{$src, $dst|$dst, $src}",
+ []>;
let neverHasSideEffects = 1 in
-def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg, (outs GR64:$dst), (ins VR64:$src),
+def MMX_MOVD64from64rr : MMXRI<0x7E, MRMSrcReg,
+ (outs GR64:$dst), (ins VR64:$src),
"movd\t{$src, $dst|$dst, $src}", []>;
let neverHasSideEffects = 1 in
@@ -187,6 +189,10 @@
(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
MOVL_shuffle_mask)))]>;
+let neverHasSideEffects = 1 in
+def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMDestMem, (outs FR64:$dst), (ins VR64:$src),
+ "movq2dq\t{$src, $dst|$dst, $src}", []>;
+
def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movntq\t{$src, $dst|$dst, $src}",
[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
@@ -575,9 +581,17 @@
(MMX_MOVD64from64rr VR64:$src)>;
def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
(MMX_MOVD64from64rr VR64:$src)>;
+def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
+ (MMX_MOVQ2FR64rr VR64:$src)>;
+def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
+ (MMX_MOVQ2FR64rr VR64:$src)>;
+def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
+ (MMX_MOVQ2FR64rr VR64:$src)>;
+def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
+ (MMX_MOVQ2FR64rr VR64:$src)>;
-// Move scalar to XMM zero-extended
-// movd to XMM register zero-extends
+// Move scalar to MMX zero-extended
+// movd to MMX register zero-extends
let AddedComplexity = 15 in {
def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))))),
(MMX_MOVZDI2PDIrr GR32:$src)>;
@@ -667,7 +681,13 @@
(MMX_PANDNrm VR64:$src1, addr:$src2)>;
// Move MMX to lower 64-bit of XMM
-def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
+def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
+ (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
+def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
+ (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
+def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
+ (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
+def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
// Move lower 64-bit of XMM to MMX.
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/ret-mmx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/ret-mmx.ll?rev=65351&r1=65350&r2=65351&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/ret-mmx.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/ret-mmx.ll Mon Feb 23 17:58:39 2009
@@ -10,8 +10,17 @@
ret void
}
+declare <1 x i64> @return_v1di()
+
define <1 x i64> @t2() nounwind {
ret <1 x i64> <i64 1>
}
-declare <1 x i64> @return_v1di()
+define <2 x i32> @t3() nounwind {
+ ret <2 x i32> <i32 1, i32 0>
+}
+
+define double @t4() nounwind {
+ ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
+}
+
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