[llvm-commits] [llvm] r64827 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Scott Michel
scottm at aero.org
Tue Feb 17 14:15:04 PST 2009
Author: pingbak
Date: Tue Feb 17 16:15:04 2009
New Revision: 64827
URL: http://llvm.org/viewvc/llvm-project?rev=64827&view=rev
Log:
Remove trailing whitespace to reduce later commit patch noise.
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Feb 17 16:15:04 2009
@@ -143,7 +143,7 @@
///
void viewGraph(const std::string &Title);
void viewGraph();
-
+
#ifndef NDEBUG
std::map<const SDNode *, std::string> NodeGraphAttrs;
#endif
@@ -151,15 +151,15 @@
/// clearGraphAttrs - Clear all previously defined node graph attributes.
/// Intended to be used from a debugging tool (eg. gdb).
void clearGraphAttrs();
-
+
/// setGraphAttrs - Set graph attributes for a node. (eg. "color=red".)
///
void setGraphAttrs(const SDNode *N, const char *Attrs);
-
+
/// getGraphAttrs - Get graph attributes for a node. (eg. "color=red".)
/// Used from getNodeAttributes.
const std::string getGraphAttrs(const SDNode *N) const;
-
+
/// setGraphColor - Convenience for setting node color attribute.
///
void setGraphColor(const SDNode *N, const char *Color);
@@ -177,7 +177,7 @@
ilist<SDNode>::size_type allnodes_size() const {
return AllNodes.size();
}
-
+
/// getRoot - Return the root tag of the SelectionDAG.
///
const SDValue &getRoot() const { return Root; }
@@ -233,7 +233,7 @@
SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4);
SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
-
+
/// getNodeValueTypes - These are obsolete, use getVTList instead.
const MVT *getNodeValueTypes(MVT VT) {
return getVTList(VT).VTs;
@@ -250,8 +250,8 @@
const MVT *getNodeValueTypes(const std::vector<MVT> &vtList) {
return getVTList(&vtList[0], (unsigned)vtList.size()).VTs;
}
-
-
+
+
//===--------------------------------------------------------------------===//
// Node creation methods.
//
@@ -320,7 +320,7 @@
SDValue getRegister(unsigned Reg, MVT VT);
SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
Value *CU);
- SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
+ SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
unsigned LabelID);
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
@@ -345,13 +345,13 @@
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
}
-
+
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2);
}
-
+
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
@@ -373,7 +373,7 @@
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
-
+
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
@@ -383,7 +383,7 @@
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Op };
- return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
+ return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
VTs, 2, Ops, 2);
}
@@ -399,7 +399,7 @@
Ops.push_back(Op2);
Ops.push_back(InFlag);
return getNode(ISD::CALLSEQ_END, DebugLoc::getUnknownLoc(), NodeTys,
- &Ops[0],
+ &Ops[0],
(unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0));
}
@@ -487,15 +487,15 @@
return getNode(ISD::SELECT_CC, DL, True.getValueType(),
LHS, RHS, True, False, getCondCode(Cond));
}
-
+
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
SDValue SV);
- /// getAtomic - Gets a node for an atomic op, produces result and chain and
+ /// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 3 operands
- SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
+ SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
@@ -585,7 +585,7 @@
SDValue Op3, SDValue Op4, SDValue Op5);
SDValue UpdateNodeOperands(SDValue N,
const SDValue *Ops, unsigned NumOps);
-
+
/// SelectNodeTo - These are used for target selectors to *mutate* the
/// specified node to have the specified return type, Target opcode, and
/// operands. Note that target opcodes are stored as
@@ -649,14 +649,14 @@
/// the current one.
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1, SDValue Op2);
@@ -680,7 +680,7 @@
/// else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
-
+
/// DAGUpdateListener - Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
/// to handle the various sorts of updates that happen.
@@ -695,12 +695,12 @@
/// NodeUpdated - The node N that was updated.
virtual void NodeUpdated(SDNode *N) = 0;
};
-
+
/// RemoveDeadNode - Remove the specified node from the system. If any of its
/// operands then becomes dead, remove them as well. Inform UpdateListener
/// for each node deleted.
void RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener = 0);
-
+
/// RemoveDeadNodes - This method deletes the unreachable nodes in the
/// given list, and any nodes that become unreachable as a result.
void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes,
@@ -711,7 +711,7 @@
/// version if 'From' is known to have a single result, use the second
/// if you have two nodes with identical results, use the third otherwise.
///
- /// These methods all take an optional UpdateListener, which (if not null) is
+ /// These methods all take an optional UpdateListener, which (if not null) is
/// informed about nodes that are deleted and modified due to recursive
/// changes in the dag.
///
@@ -768,7 +768,7 @@
case ISD::AND:
case ISD::OR:
case ISD::XOR:
- case ISD::ADDC:
+ case ISD::ADDC:
case ISD::ADDE: return true;
default: return false;
}
@@ -785,7 +785,7 @@
/// either of the specified value types.
SDValue CreateStackTemporary(MVT VT1, MVT VT2);
- /// FoldConstantArithmetic -
+ /// FoldConstantArithmetic -
SDValue FoldConstantArithmetic(unsigned Opcode,
MVT VT,
ConstantSDNode *Cst1,
@@ -794,7 +794,7 @@
/// FoldSetCC - Constant fold a setcc to true or false.
SDValue FoldSetCC(MVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond, DebugLoc dl);
-
+
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
/// use this predicate to simplify operations downstream.
bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
@@ -804,11 +804,11 @@
/// known to be the same type.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
const;
-
+
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
- /// processing. Targets can implement the computeMaskedBitsForTargetNode
+ /// processing. Targets can implement the computeMaskedBitsForTargetNode
/// method in the TargetLowering class to allow target nodes to be understood.
void ComputeMaskedBits(SDValue Op, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, unsigned Depth = 0) const;
@@ -829,7 +829,7 @@
/// getShuffleScalarElt - Returns the scalar element that will make up the ith
/// element of the result of the vector shuffle.
SDValue getShuffleScalarElt(const SDNode *N, unsigned Idx);
-
+
private:
bool RemoveNodeFromCSEMaps(SDNode *N);
void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListener);
@@ -845,10 +845,10 @@
unsigned getMVTAlignment(MVT MemoryVT) const;
void allnodes_clear();
-
+
/// VTList - List of non-single value types.
std::vector<SDVTList> VTList;
-
+
/// CondCodeNodes - Maps to auto-CSE operations.
std::vector<CondCodeSDNode*> CondCodeNodes;
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Feb 17 16:15:04 2009
@@ -78,7 +78,7 @@
// DELETED_NODE - This is an illegal flag value that is used to catch
// errors. This opcode is not a legal opcode for any node.
DELETED_NODE,
-
+
// EntryToken - This is the marker used to indicate the start of the region.
EntryToken,
@@ -86,10 +86,10 @@
// single token result. This is used to represent the fact that the operand
// operators are independent of each other.
TokenFactor,
-
- // AssertSext, AssertZext - These nodes record if a register contains a
- // value that has already been zero or sign extended from a narrower type.
- // These nodes take two operands. The first is the node that has already
+
+ // AssertSext, AssertZext - These nodes record if a register contains a
+ // value that has already been zero or sign extended from a narrower type.
+ // These nodes take two operands. The first is the node that has already
// been extended, and the second is a value type node indicating the width
// of the extension
AssertSext, AssertZext,
@@ -102,7 +102,7 @@
// The address of the GOT
GLOBAL_OFFSET_TABLE,
-
+
// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
// llvm.returnaddress on the DAG. These nodes take one operand, the index
// of the frame or return address to return. An index of zero corresponds
@@ -114,11 +114,11 @@
// first (possible) on-stack argument. This is needed for correct stack
// adjustment during unwind.
FRAME_TO_ARGS_OFFSET,
-
+
// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the
// address of the exception block on entry to an landing pad block.
EXCEPTIONADDR,
-
+
// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents
// the selection index of the exception thrown.
EHSELECTION,
@@ -133,7 +133,7 @@
// simplification of the constant.
TargetConstant,
TargetConstantFP,
-
+
// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
// anything else with this node, and this is valid in the target-specific
// dag, turning into a GlobalAddress operand.
@@ -143,14 +143,14 @@
TargetJumpTable,
TargetConstantPool,
TargetExternalSymbol,
-
+
/// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
/// This node represents a target intrinsic function with no side effects.
/// The first operand is the ID number of the intrinsic from the
/// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
/// node has returns the result of the intrinsic.
INTRINSIC_WO_CHAIN,
-
+
/// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
/// This node represents a target intrinsic function with side effects that
/// returns a result. The first operand is a chain pointer. The second is
@@ -165,9 +165,9 @@
/// second is the ID number of the intrinsic from the llvm::Intrinsic
/// namespace. The operands to the intrinsic follow.
INTRINSIC_VOID,
-
+
// CopyToReg - This node has three operands: a chain, a register number to
- // set to this value, and a value.
+ // set to this value, and a value.
CopyToReg,
// CopyFromReg - This node indicates that the input value is a virtual or
@@ -177,7 +177,7 @@
// UNDEF - An undefined node
UNDEF,
-
+
/// FORMAL_ARGUMENTS(CHAIN, CC#, ISVARARG, FLAG0, ..., FLAGn) - This node
/// represents the formal arguments for a function. CC# is a Constant value
/// indicating the calling convention of the function, and ISVARARG is a
@@ -185,9 +185,9 @@
/// has one result value for each incoming argument, plus one for the output
/// chain. It must be custom legalized. See description of CALL node for
/// FLAG argument contents explanation.
- ///
+ ///
FORMAL_ARGUMENTS,
-
+
/// RV1, RV2...RVn, CHAIN = CALL(CHAIN, CALLEE,
/// ARG0, FLAG0, ARG1, FLAG1, ... ARGn, FLAGn)
/// This node represents a fully general function call, before the legalizer
@@ -239,17 +239,17 @@
// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
// remainder result.
SDIVREM, UDIVREM,
-
+
// CARRY_FALSE - This node is used when folding other nodes,
// like ADDC/SUBC, which indicate the carry result is always false.
CARRY_FALSE,
-
+
// Carry-setting nodes for multiple precision addition and subtraction.
// These nodes take two operands of the same value type, and produce two
// results. The first result is the normal add or sub result, the second
// result is the carry flag result.
ADDC, SUBC,
-
+
// Carry-using nodes for multiple precision addition and subtraction. These
// nodes take three operands: The first two are the normal lhs and rhs to
// the add or sub, and the third is the input carry flag. These nodes
@@ -286,12 +286,12 @@
// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
// value as an integer 0/1 value.
FGETSIGN,
-
+
/// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector
/// with the specified, possibly variable, elements. The number of elements
/// is required to be a power of two.
BUILD_VECTOR,
-
+
/// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
/// at IDX replaced with VAL. If the type of VAL is larger than the vector
/// element type then VAL is truncated before replacement.
@@ -300,13 +300,13 @@
/// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
/// identified by the (potentially variable) element number IDX.
EXTRACT_VECTOR_ELT,
-
+
/// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
/// vector type with the same length and element type, this produces a
/// concatenated vector result value, with length equal to the sum of the
/// lengths of the input vectors.
CONCAT_VECTORS,
-
+
/// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
/// vector value) starting with the (potentially variable) element number
/// IDX, which must be a multiple of the result vector length.
@@ -325,19 +325,19 @@
/// scalar value into element 0 of the resultant vector type. The top
/// elements 1 to N-1 of the N-element vector are undefined.
SCALAR_TO_VECTOR,
-
- // EXTRACT_SUBREG - This node is used to extract a sub-register value.
+
+ // EXTRACT_SUBREG - This node is used to extract a sub-register value.
// This node takes a superreg and a constant sub-register index as operands.
// Note sub-register indices must be increasing. That is, if the
// sub-register index of a 8-bit sub-register is N, then the index for a
// 16-bit sub-register must be at least N+1.
EXTRACT_SUBREG,
-
- // INSERT_SUBREG - This node is used to insert a sub-register value.
+
+ // INSERT_SUBREG - This node is used to insert a sub-register value.
// This node takes a superreg, a subreg value, and a constant sub-register
// index as operands.
INSERT_SUBREG,
-
+
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*N], then return the top part.
MULHU, MULHS,
@@ -354,9 +354,9 @@
// i1 then the high bits must conform to getBooleanContents.
SELECT,
- // Select with condition operator - This selects between a true value and
+ // Select with condition operator - This selects between a true value and
// a false value (ops #2 and #3) based on the boolean result of comparing
- // the lhs and rhs (ops #0 and #1) of a conditional expression with the
+ // the lhs and rhs (ops #0 and #1) of a conditional expression with the
// condition code in op #4, a CondCodeSDNode.
SELECT_CC,
@@ -369,7 +369,7 @@
// Vector SetCC operator - This evaluates to a vector of integer elements
// with the high bit in each element set to true if the comparison is true
- // and false if the comparison is false. All other bits in each element
+ // and false if the comparison is false. All other bits in each element
// are undefined. The operands to this are the left and right operands
// to compare (ops #0, and #1) and the condition code to compare them with
// (op #2) as a CondCodeSDNode.
@@ -395,7 +395,7 @@
// ANY_EXTEND - Used for integer types. The high bits are undefined.
ANY_EXTEND,
-
+
// TRUNCATE - Completely drop the high bits.
TRUNCATE,
@@ -425,10 +425,10 @@
/// The TRUNC = 1 case is used in cases where we know that the value will
/// not be modified by the node, because Y is not using any of the extra
/// precision of source type. This allows certain transformations like
- /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
+ /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
/// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
FP_ROUND,
-
+
// FLT_ROUNDS_ - Returns current rounding mode:
// -1 Undefined
// 0 Round to 0
@@ -449,12 +449,12 @@
// BIT_CONVERT - Theis operator converts between integer and FP values, as
// if one was stored to memory as integer and the other was loaded from the
- // same address (or equivalently for vector format conversions, etc). The
- // source and result are required to have the same bit size (e.g.
- // f32 <-> i32). This can also be used for int-to-int or fp-to-fp
+ // same address (or equivalently for vector format conversions, etc). The
+ // source and result are required to have the same bit size (e.g.
+ // f32 <-> i32). This can also be used for int-to-int or fp-to-fp
// conversions, but that is a noop, deleted by getNode().
BIT_CONVERT,
-
+
// CONVERT_RNDSAT - This operator is used to support various conversions
// between various types (float, signed, unsigned and vectors of those
// types) with rounding and saturation. NOTE: Avoid using this operator as
@@ -467,7 +467,7 @@
// 4) saturation imm
// 5) ISD::CvtCode indicating the type of conversion to do
CONVERT_RNDSAT,
-
+
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
@@ -475,7 +475,7 @@
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
FLOG, FLOG2, FLOG10, FEXP, FEXP2,
FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
-
+
// LOAD and STORE have token chains as their first operand, then the same
// operands as an LLVM load/store instruction, then an offset node that
// is added / subtracted from the base pointer to form the address (for
@@ -517,7 +517,7 @@
// compare, rather than as a combined SetCC node. The operands in order are
// chain, cc, lhs, rhs, block to branch to if condition is true.
BR_CC,
-
+
// RET - Return from function. The first operand is the chain,
// and any subsequent operands are pairs of return value and return value
// attributes (see CALL for description of attributes) for the function.
@@ -532,7 +532,7 @@
// Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
// Operand #last: Optional, an incoming flag.
INLINEASM,
-
+
// DBG_LABEL, EH_LABEL - Represents a label in mid basic block used to track
// locations needed for debug and exception handling tables. These nodes
// take a chain as input and return a chain.
@@ -544,16 +544,16 @@
// a chain, while the next two operands are first two arguments (address
// and variable) of a llvm.dbg.declare instruction.
DECLARE,
-
+
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
// value, the same type as the pointer type for the system, and an output
// chain.
STACKSAVE,
-
+
// STACKRESTORE has two operands, an input chain and a pointer to restore to
// it returns an output chain.
STACKRESTORE,
-
+
// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of
// a call sequence, and carry arbitrary information that target might want
// to know. The first operand is a chain, the rest are specified by the
@@ -561,16 +561,16 @@
// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
CALLSEQ_START, // Beginning of a call sequence
CALLSEQ_END, // End of a call sequence
-
- // VAARG - VAARG has three operands: an input chain, a pointer, and a
+
+ // VAARG - VAARG has three operands: an input chain, a pointer, and a
// SRCVALUE. It returns a pair of values: the vaarg value and a new chain.
VAARG,
-
+
// VACOPY - VACOPY has five operands: an input chain, a destination pointer,
// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
// source.
VACOPY,
-
+
// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a
// pointer, and a SRCVALUE.
VAEND, VASTART,
@@ -589,7 +589,7 @@
// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
// The only operand is a chain and a value and a chain are produced. The
- // value is the contents of the architecture specific cycle counter like
+ // value is the contents of the architecture specific cycle counter like
// register (or other high accuracy low latency clock source)
READCYCLECOUNTER,
@@ -601,7 +601,7 @@
// column number, and a pointer to a CompileUnit object identifying
// the containing compilation unit. It produces a token chain as output.
DBG_STOPPOINT,
-
+
// DEBUG_LOC - This node is used to represent source line information
// embedded in the code. It takes a token chain as input, then a line
// number, then a column then a file id (provided by MachineModuleInfo.) It
@@ -625,7 +625,7 @@
// read / write specifier, and locality specifier.
PREFETCH,
- // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
+ // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
// store-store, device)
// This corresponds to the memory.barrier intrinsic.
// it takes an input chain, 4 operands to specify the type of barrier, an
@@ -659,7 +659,7 @@
ATOMIC_LOAD_MAX,
ATOMIC_LOAD_UMIN,
ATOMIC_LOAD_UMAX,
-
+
// BUILTIN_OP_END - This must be the last enum value in this list.
BUILTIN_OP_END
};
@@ -682,9 +682,9 @@
/// isDebugLabel - Return true if the specified node represents a debug
/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool isDebugLabel(const SDNode *N);
-
+
//===--------------------------------------------------------------------===//
- /// MemIndexedMode enum - This enum defines the load / store indexed
+ /// MemIndexedMode enum - This enum defines the load / store indexed
/// addressing modes.
///
/// UNINDEXED "Normal" load / store. The effective address is already
@@ -729,7 +729,7 @@
/// integer result type.
/// ZEXTLOAD loads the integer operand and zero extends it to a larger
/// integer result type.
- /// EXTLOAD is used for three things: floating point extending loads,
+ /// EXTLOAD is used for three things: floating point extending loads,
/// integer extending loads [the top bits are undefined], and vector
/// extending loads [load into low elt].
///
@@ -834,7 +834,7 @@
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
//===--------------------------------------------------------------------===//
- /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
+ /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
/// supports.
enum CvtCode {
CVT_FF, // Float from Float
@@ -915,15 +915,15 @@
inline unsigned getMachineOpcode() const;
inline const DebugLoc getDebugLoc() const;
-
+
/// reachesChainWithoutSideEffects - Return true if this operand (which must
- /// be a chain) reaches the specified operand without crossing any
+ /// be a chain) reaches the specified operand without crossing any
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
- bool reachesChainWithoutSideEffects(SDValue Dest,
+ bool reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth = 2) const;
-
+
/// use_empty - Return true if there are no nodes using value ResNo
/// of Node.
///
@@ -937,10 +937,10 @@
template<> struct DenseMapInfo<SDValue> {
- static inline SDValue getEmptyKey() {
- return SDValue((SDNode*)-1, -1U);
+ static inline SDValue getEmptyKey() {
+ return SDValue((SDNode*)-1, -1U);
}
- static inline SDValue getTombstoneKey() {
+ static inline SDValue getTombstoneKey() {
return SDValue((SDNode*)-1, 0);
}
static unsigned getHashValue(const SDValue &Val) {
@@ -978,7 +978,7 @@
SDValue Val;
/// User - The user of this value.
SDNode *User;
- /// Prev, Next - Pointers to the uses list of the SDNode referred by
+ /// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev, *Next;
@@ -994,7 +994,7 @@
/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }
-
+
/// getUser - This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }
@@ -1012,7 +1012,7 @@
bool operator==(const SDValue &V) const {
return Val == V;
}
-
+
/// operator!= - Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
return Val != V;
@@ -1075,7 +1075,7 @@
/// NodeType - The operation that this node performs.
///
short NodeType;
-
+
/// OperandsNeedDelete - This is true if OperandList was new[]'d. If true,
/// then they will be delete[]'d when the node is destroyed.
unsigned short OperandsNeedDelete : 1;
@@ -1093,7 +1093,7 @@
/// OperandList - The values that are used by this operation.
///
SDUse *OperandList;
-
+
/// ValueList - The types of the values this node defines. SDNode's may
/// define multiple values simultaneously.
const MVT *ValueList;
@@ -1170,7 +1170,7 @@
void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
/// use_iterator - This class provides iterator support for SDUse
- /// operands that use a specific SDNode.
+ /// operands that use a specific SDNode.
class use_iterator
: public forward_iterator<SDUse, ptrdiff_t> {
SDUse *Op;
@@ -1190,7 +1190,7 @@
bool operator!=(const use_iterator &x) const {
return !operator==(x);
}
-
+
/// atEnd - return true if this iterator is at the end of uses list.
bool atEnd() const { return Op == 0; }
@@ -1260,7 +1260,7 @@
///
unsigned getNumOperands() const { return NumOperands; }
- /// getConstantOperandVal - Helper method returns the integer value of a
+ /// getConstantOperandVal - Helper method returns the integer value of a
/// ConstantSDNode operand.
uint64_t getConstantOperandVal(unsigned Num) const;
@@ -1353,7 +1353,7 @@
return Ret;
}
- SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
+ SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
unsigned NumOps)
: NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
NodeId(-1),
@@ -1374,7 +1374,7 @@
NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL),
NumOperands(0), NumValues(VTs.NumVTs),
debugLoc(dl) {}
-
+
/// InitOperands - Initialize the operands list of this with 1 operand.
void InitOperands(SDUse *Ops, const SDValue &Op0) {
Ops[0].setUser(this);
@@ -1545,7 +1545,7 @@
getSDVTList(MVT::Other)) {
InitOperands(&Op, X);
}
- ~HandleSDNode();
+ ~HandleSDNode();
const SDValue &getValue() const { return Op; }
};
@@ -1713,7 +1713,7 @@
protected:
friend class SelectionDAG;
ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT)
- : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
+ : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
public:
@@ -1752,7 +1752,7 @@
/// two floating point values.
/// We leave the version with the double argument here because it's just so
- /// convenient to write "2.0" and the like. Without this function we'd
+ /// convenient to write "2.0" and the like. Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
bool ignored;
@@ -1770,7 +1770,7 @@
static bool classof(const ConstantFPSDNode *) { return true; }
static bool classof(const SDNode *N) {
- return N->getOpcode() == ISD::ConstantFP ||
+ return N->getOpcode() == ISD::ConstantFP ||
N->getOpcode() == ISD::TargetConstantFP;
}
};
@@ -1801,7 +1801,7 @@
protected:
friend class SelectionDAG;
FrameIndexSDNode(int fi, MVT VT, bool isTarg)
- : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
+ : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) {
}
public:
@@ -1824,9 +1824,9 @@
DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti) {
}
public:
-
+
int getIndex() const { return JTI; }
-
+
static bool classof(const JumpTableSDNode *) { return true; }
static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::JumpTable ||
@@ -1859,7 +1859,7 @@
}
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT VT, int o=0)
- : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
@@ -1894,7 +1894,7 @@
int getOffset() const {
return Offset & ~(1 << (sizeof(unsigned)*8-1));
}
-
+
// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or log2 of the desired value.
unsigned getAlignment() const { return Alignment; }
@@ -2087,7 +2087,7 @@
friend class SelectionDAG;
explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops,
unsigned NumOps, ISD::CvtCode Code)
- : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
+ : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
CvtCode(Code) {
assert(NumOps == 5 && "wrong number of operations");
}
@@ -2150,14 +2150,14 @@
void setNest() { Flags |= One << NestOffs; }
unsigned getByValAlign() const {
- return (unsigned)
+ return (unsigned)
((One << ((Flags & ByValAlign) >> ByValAlignOffs)) / 2);
}
void setByValAlign(unsigned A) {
Flags = (Flags & ~ByValAlign) |
(uint64_t(Log2_32(A) + 1) << ByValAlignOffs);
}
-
+
bool isSplit() const { return Flags & Split; }
void setSplit() { Flags |= One << SplitOffs; }
@@ -2214,8 +2214,8 @@
bool Inreg;
protected:
friend class SelectionDAG;
- CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
- bool isinreg, SDVTList VTs, const SDValue *Operands,
+ CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
+ bool isinreg, SDVTList VTs, const SDValue *Operands,
unsigned numOperands)
: SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 17 16:15:04 2009
@@ -9,7 +9,7 @@
//
// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
// both before and after the DAG is legalized.
-//
+//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "dagcombine"
@@ -89,14 +89,14 @@
WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
WorkList.end());
}
-
+
SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
bool AddTo = true);
-
+
SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
return CombineTo(N, &Res, 1, AddTo);
}
-
+
SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
bool AddTo = true) {
SDValue To[] = { Res0, Res1 };
@@ -104,9 +104,9 @@
}
void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
-
- private:
-
+
+ private:
+
/// SimplifyDemandedBits - Check the specified integer node value to see if
/// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
@@ -119,8 +119,8 @@
bool CombineToPreIndexedLoadStore(SDNode *N);
bool CombineToPostIndexedLoadStore(SDNode *N);
-
-
+
+
/// combine - call the node-specific routine that knows how to fold each
/// particular type of node. If that doesn't do anything, try the
/// target-specific DAG combines.
@@ -197,18 +197,18 @@
SDValue XformToShuffleWithZero(SDNode *N);
SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
-
+
SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
- SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
- SDValue N3, ISD::CondCode CC,
+ SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
+ SDValue N3, ISD::CondCode CC,
bool NotExtCompare = false);
SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans = true);
- SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
+ SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
@@ -216,9 +216,9 @@
SDValue BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
SDValue ReduceLoadWidth(SDNode *N);
-
+
SDValue GetDemandedBits(SDValue V, const APInt &Mask);
-
+
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
/// looking for aliasing nodes and adding them to the Aliases vector.
void GatherAllAliases(SDNode *N, SDValue OriginalChain,
@@ -230,13 +230,13 @@
const Value *SrcValue1, int SrcValueOffset1,
SDValue Ptr2, int64_t Size2,
const Value *SrcValue2, int SrcValueOffset2) const;
-
+
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
bool FindAliasInfo(SDNode *N,
SDValue &Ptr, int64_t &Size,
const Value *&SrcValue, int &SrcValueOffset) const;
-
+
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
/// looking for a better chain (aliasing node.)
SDValue FindBetterChain(SDNode *N, SDValue Chain);
@@ -256,7 +256,7 @@
LegalTypes(false),
Fast(fast),
AA(A) {}
-
+
/// Run - runs the dag combiner on all nodes in the work list
void Run(CombineLevel AtLevel);
};
@@ -266,16 +266,16 @@
namespace {
/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
/// nodes from the worklist.
-class VISIBILITY_HIDDEN WorkListRemover :
+class VISIBILITY_HIDDEN WorkListRemover :
public SelectionDAG::DAGUpdateListener {
DAGCombiner &DC;
public:
explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
-
+
virtual void NodeDeleted(SDNode *N, SDNode *E) {
DC.removeFromWorkList(N);
}
-
+
virtual void NodeUpdated(SDNode *N) {
// Ignore updates.
}
@@ -326,13 +326,13 @@
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return 2;
-
+
// Don't allow anything with multiple uses.
if (!Op.hasOneUse()) return 0;
-
+
// Don't recurse exponentially.
if (Depth > 6) return 0;
-
+
switch (Op.getOpcode()) {
default: return false;
case ISD::ConstantFP:
@@ -342,29 +342,29 @@
case ISD::FADD:
// FIXME: determine better conditions for this xform.
if (!UnsafeFPMath) return 0;
-
+
// fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
return V;
// fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
case ISD::FSUB:
- // We can't turn -(A-B) into B-A when we honor signed zeros.
+ // We can't turn -(A-B) into B-A when we honor signed zeros.
if (!UnsafeFPMath) return 0;
-
+
// fold (fneg (fsub A, B)) -> (fsub B, A)
return 1;
-
+
case ISD::FMUL:
case ISD::FDIV:
if (HonorSignDependentRoundingFPMath()) return 0;
-
+
// fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
return V;
-
+
return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
-
+
case ISD::FP_EXTEND:
case ISD::FP_ROUND:
case ISD::FSIN:
@@ -378,10 +378,10 @@
bool LegalOperations, unsigned Depth = 0) {
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
-
+
// Don't allow anything with multiple uses.
assert(Op.hasOneUse() && "Unknown reuse!");
-
+
assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
switch (Op.getOpcode()) {
default: assert(0 && "Unknown code");
@@ -393,56 +393,56 @@
case ISD::FADD:
// FIXME: determine better conditions for this xform.
assert(UnsafeFPMath);
-
+
// fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG,
+ GetNegatedExpression(Op.getOperand(0), DAG,
LegalOperations, Depth+1),
Op.getOperand(1));
// fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(1), DAG,
+ GetNegatedExpression(Op.getOperand(1), DAG,
LegalOperations, Depth+1),
Op.getOperand(0));
case ISD::FSUB:
- // We can't turn -(A-B) into B-A when we honor signed zeros.
+ // We can't turn -(A-B) into B-A when we honor signed zeros.
assert(UnsafeFPMath);
// fold (fneg (fsub 0, B)) -> B
if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
if (N0CFP->getValueAPF().isZero())
return Op.getOperand(1);
-
+
// fold (fneg (fsub A, B)) -> (fsub B, A)
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
Op.getOperand(1), Op.getOperand(0));
-
+
case ISD::FMUL:
case ISD::FDIV:
assert(!HonorSignDependentRoundingFPMath());
-
+
// fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG,
+ GetNegatedExpression(Op.getOperand(0), DAG,
LegalOperations, Depth+1),
Op.getOperand(1));
-
+
// fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
Op.getOperand(0),
GetNegatedExpression(Op.getOperand(1), DAG,
LegalOperations, Depth+1));
-
+
case ISD::FP_EXTEND:
case ISD::FSIN:
return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG,
+ GetNegatedExpression(Op.getOperand(0), DAG,
LegalOperations, Depth+1));
case ISD::FP_ROUND:
return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG,
+ GetNegatedExpression(Op.getOperand(0), DAG,
LegalOperations, Depth+1),
Op.getOperand(1));
}
@@ -451,7 +451,7 @@
// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
// that selects between the values 1 and 0, making it equivalent to a setcc.
-// Also, set the incoming LHS, RHS, and CC references to the appropriate
+// Also, set the incoming LHS, RHS, and CC references to the appropriate
// nodes based on the type of node we are checking. This simplifies life a
// bit for the callers.
static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
@@ -462,7 +462,7 @@
CC = N.getOperand(2);
return true;
}
- if (N.getOpcode() == ISD::SELECT_CC &&
+ if (N.getOpcode() == ISD::SELECT_CC &&
N.getOperand(2).getOpcode() == ISD::Constant &&
N.getOperand(3).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
@@ -537,7 +537,7 @@
"Cannot combine value to value of different type!"));
WorkListRemover DeadNodes(*this);
DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
-
+
if (AddTo) {
// Push the new nodes and any users onto the worklist
for (unsigned i = 0, e = NumTo; i != e; ++i) {
@@ -545,7 +545,7 @@
AddUsersToWorkList(To[i].getNode());
}
}
-
+
// Finally, if the node is now dead, remove it from the graph. The node
// may not be dead if the replacement process recursively simplified to
// something else needing this node.
@@ -553,7 +553,7 @@
// Nodes can be reintroduced into the worklist. Make sure we do not
// process a node that has been replaced.
removeFromWorkList(N);
-
+
// Finally, since the node is now dead, remove it from the graph.
DAG.DeleteNode(N);
}
@@ -563,7 +563,7 @@
void
DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
TLO) {
- // Replace all uses. If any nodes become isomorphic to other nodes and
+ // Replace all uses. If any nodes become isomorphic to other nodes and
// are deleted, make sure to remove them from our worklist.
WorkListRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
@@ -571,19 +571,19 @@
// Push the new node and any (possibly new) users onto the worklist.
AddToWorkList(TLO.New.getNode());
AddUsersToWorkList(TLO.New.getNode());
-
+
// Finally, if the node is now dead, remove it from the graph. The node
// may not be dead if the replacement process recursively simplified to
// something else needing this node.
if (TLO.Old.getNode()->use_empty()) {
removeFromWorkList(TLO.Old.getNode());
-
+
// If the operands of this node are only used by the node, they will now
// be dead. Make sure to visit them first to delete dead nodes early.
for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
-
+
DAG.DeleteNode(TLO.Old.getNode());
}
}
@@ -596,16 +596,16 @@
APInt KnownZero, KnownOne;
if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
return false;
-
+
// Revisit the node.
AddToWorkList(Op.getNode());
-
+
// Replace the old value with the new one.
++NodesCombined;
DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
DOUT << '\n';
-
+
CommitTargetLoweringOpt(TLO);
return true;
}
@@ -630,42 +630,42 @@
// to the root node, preventing it from being deleted, and tracking any
// changes of the root.
HandleSDNode Dummy(DAG.getRoot());
-
+
// The root of the dag may dangle to deleted nodes until the dag combiner is
// done. Set it to null to avoid confusion.
DAG.setRoot(SDValue());
-
+
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
while (!WorkList.empty()) {
SDNode *N = WorkList.back();
WorkList.pop_back();
-
+
// If N has no uses, it is dead. Make sure to revisit all N's operands once
// N is deleted from the DAG, since they too may now be dead or may have a
// reduced number of uses, allowing other xforms.
if (N->use_empty() && N != &Dummy) {
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
AddToWorkList(N->getOperand(i).getNode());
-
+
DAG.DeleteNode(N);
continue;
}
-
+
SDValue RV = combine(N);
-
+
if (RV.getNode() == 0)
continue;
-
+
++NodesCombined;
-
+
// If we get back the same node we passed in, rather than a new node or
// zero, we know that the node must have defined multiple values and
- // CombineTo was used. Since CombineTo takes care of the worklist
+ // CombineTo was used. Since CombineTo takes care of the worklist
// mechanics for us, we have no work to do in this case.
if (RV.getNode() == N)
continue;
-
+
assert(N->getOpcode() != ISD::DELETED_NODE &&
RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
"Node was deleted but visit returned new node!");
@@ -682,17 +682,17 @@
SDValue OpV = RV;
DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
}
-
+
// Push the new node and any users onto the worklist
AddToWorkList(RV.getNode());
AddUsersToWorkList(RV.getNode());
-
+
// Add any uses of the old node to the worklist in case this node is the
// last one that uses them. They may become dead after this node is
// deleted.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
AddToWorkList(N->getOperand(i).getNode());
-
+
// Finally, if the node is now dead, remove it from the graph. The node
// may not be dead if the replacement process recursively simplified to
// something else needing this node.
@@ -700,12 +700,12 @@
// Nodes can be reintroduced into the worklist. Make sure we do not
// process a node that has been replaced.
removeFromWorkList(N);
-
+
// Finally, since the node is now dead, remove it from the graph.
DAG.DeleteNode(N);
}
}
-
+
// If the root changed (e.g. it was a dead load, update the root).
DAG.setRoot(Dummy.getValue());
}
@@ -789,16 +789,16 @@
TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
// Expose the DAG combiner to the target combiner impls.
- TargetLowering::DAGCombinerInfo
+ TargetLowering::DAGCombinerInfo
DagCombineInfo(DAG, Level == Unrestricted, false, this);
RV = TLI.PerformDAGCombine(N, DagCombineInfo);
}
}
- // If N is a commutative binary node, try commuting it to enable more
+ // If N is a commutative binary node, try commuting it to enable more
// sdisel CSE.
- if (RV.getNode() == 0 &&
+ if (RV.getNode() == 0 &&
SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
N->getNumValues() == 1) {
SDValue N0 = N->getOperand(0);
@@ -815,7 +815,7 @@
}
return RV;
-}
+}
/// getInputChainForNode - Given a node, return its input chain if it has one,
/// otherwise return a null sd operand.
@@ -841,31 +841,31 @@
if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
return N->getOperand(1);
}
-
+
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
- SmallPtrSet<SDNode*, 16> SeenOps;
+ SmallPtrSet<SDNode*, 16> SeenOps;
bool Changed = false; // If we should replace this token factor.
-
+
// Start out with this token factor.
TFs.push_back(N);
-
+
// Iterate through token factors. The TFs grows when new token factors are
// encountered.
for (unsigned i = 0; i < TFs.size(); ++i) {
SDNode *TF = TFs[i];
-
+
// Check each of the operands.
for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
SDValue Op = TF->getOperand(i);
-
+
switch (Op.getOpcode()) {
case ISD::EntryToken:
// Entry tokens don't need to be added to the list. They are
// rededundant.
Changed = true;
break;
-
+
case ISD::TokenFactor:
if ((CombinerAA || Op.hasOneUse()) &&
std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
@@ -877,7 +877,7 @@
break;
}
// Fall thru
-
+
default:
// Only add if it isn't already in the list.
if (SeenOps.insert(Op.getNode()))
@@ -905,7 +905,7 @@
// Don't add users to work list.
return CombineTo(N, Result, false);
}
-
+
return Result;
}
@@ -1092,7 +1092,7 @@
if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
+
// fold (a+b) -> (a|b) iff a and b share no bits.
if (VT.isInteger() && !VT.isVector()) {
APInt LHSZero, LHSOne;
@@ -1102,7 +1102,7 @@
if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
-
+
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
@@ -1140,22 +1140,22 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
-
+
// If the flag result is dead, turn this into an ADD.
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
DAG.getNode(ISD::CARRY_FALSE,
N->getDebugLoc(), MVT::Flag));
-
+
// canonicalize constant to RHS.
if (N0C && !N1C)
return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
-
+
// fold (addc x, 0) -> x + no carry out
if (N1C && N1C->isNullValue())
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
N->getDebugLoc(), MVT::Flag));
-
+
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne;
@@ -1164,7 +1164,7 @@
if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
-
+
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
@@ -1173,7 +1173,7 @@
DAG.getNode(ISD::CARRY_FALSE,
N->getDebugLoc(), MVT::Flag));
}
-
+
return SDValue();
}
@@ -1183,16 +1183,16 @@
SDValue CarryIn = N->getOperand(2);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-
+
// canonicalize constant to RHS
if (N0C && !N1C)
return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
N1, N0, CarryIn);
-
+
// fold (adde x, y, false) -> (addc x, y)
if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
-
+
return SDValue();
}
@@ -1202,7 +1202,7 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
MVT VT = N0.getValueType();
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
@@ -1224,7 +1224,7 @@
return N0.getOperand(1);
// fold (A+B)-B -> A
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
- return N0.getOperand(0);
+ return N0.getOperand(0);
// fold ((A+(B+or-C))-B) -> A+or-C
if (N0.getOpcode() == ISD::ADD &&
(N0.getOperand(1).getOpcode() == ISD::SUB ||
@@ -1280,13 +1280,13 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (mul x, undef) -> 0
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
@@ -1310,7 +1310,7 @@
getShiftAmountTy()));
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
if (N1C && isPowerOf2_64(-N1C->getSExtValue()))
- // FIXME: If the input is something that is easily negated (e.g. a
+ // FIXME: If the input is something that is easily negated (e.g. a
// single-use add), we should put the negate there.
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
DAG.getConstant(0, VT),
@@ -1326,7 +1326,7 @@
return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
N0.getOperand(0), C3);
}
-
+
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
// use.
{
@@ -1335,7 +1335,7 @@
if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
N0.getNode()->hasOneUse()) {
Sh = N0; Y = N1;
- } else if (N1.getOpcode() == ISD::SHL &&
+ } else if (N1.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N1.getOperand(1)) &&
N1.getNode()->hasOneUse()) {
Sh = N1; Y = N0;
@@ -1350,14 +1350,14 @@
}
// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
- if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
+ if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1)))
return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
N0.getOperand(0), N1),
DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
N0.getOperand(1), N1));
-
+
// reassociate mul
SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
if (RMUL.getNode() != 0)
@@ -1378,7 +1378,7 @@
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (sdiv c1, c2) -> c1/c2
if (N0C && N1C && !N1C->isNullValue())
return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
@@ -1398,7 +1398,7 @@
}
// fold (sdiv X, pow2) -> simple ops after legalize
if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
- (isPowerOf2_64(N1C->getSExtValue()) ||
+ (isPowerOf2_64(N1C->getSExtValue()) ||
isPowerOf2_64(-N1C->getSExtValue()))) {
// If dividing by powers of two is cheap, then don't perform the following
// fold.
@@ -1437,7 +1437,7 @@
// if integer divide is expensive and we satisfy the requirements, emit an
// alternate sequence.
- if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
+ if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
!TLI.isIntDivCheap()) {
SDValue Op = BuildSDIV(N);
if (Op.getNode()) return Op;
@@ -1459,19 +1459,19 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
MVT VT = N->getValueType(0);
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (udiv c1, c2) -> c1/c2
if (N0C && N1C && !N1C->isNullValue())
return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
// fold (udiv x, (1 << c)) -> x >>u c
if (N1C && N1C->getAPIntValue().isPowerOf2())
- return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
+ return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
DAG.getConstant(N1C->getAPIntValue().logBase2(),
getShiftAmountTy()));
// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
@@ -1511,7 +1511,7 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold (srem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
@@ -1521,7 +1521,7 @@
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
}
-
+
// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
if (N1C && !N1C->isNullValue()) {
@@ -1536,7 +1536,7 @@
return Sub;
}
}
-
+
// undef % X -> 0
if (N0.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
@@ -1553,7 +1553,7 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold (urem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
@@ -1574,7 +1574,7 @@
}
}
}
-
+
// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
if (N1C && !N1C->isNullValue()) {
@@ -1589,7 +1589,7 @@
return Sub;
}
}
-
+
// undef % X -> 0
if (N0.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
@@ -1605,7 +1605,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold (mulhs x, 0) -> 0
if (N1C && N1C->isNullValue())
return N1;
@@ -1626,7 +1626,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold (mulhu x, 0) -> 0
if (N1C && N1C->isNullValue())
return N1;
@@ -1644,7 +1644,7 @@
/// compute two values. LoOp and HiOp give the opcodes for the two computations
/// that are being performed. Return true if a simplification was made.
///
-SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
+SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp) {
// If the high half is not needed, just compute the low half.
bool HiExists = N->hasAnyUseOfValue(1);
@@ -1713,14 +1713,14 @@
SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
if (Res.getNode()) return Res;
-
+
return SDValue();
}
SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
if (Res.getNode()) return Res;
-
+
return SDValue();
}
@@ -1730,7 +1730,7 @@
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
MVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
-
+
// For each of OP in AND/OR/XOR:
// fold (OP (zext x), (zext y)) -> (zext (OP x, y))
// fold (OP (sext x), (sext y)) -> (sext (OP x, y))
@@ -1745,7 +1745,7 @@
AddToWorkList(ORNode.getNode());
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
}
-
+
// For each of OP in SHL/SRL/SRA/AND...
// fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
// fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
@@ -1760,7 +1760,7 @@
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
ORNode, N0.getOperand(1));
}
-
+
return SDValue();
}
@@ -1772,13 +1772,13 @@
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N1.getValueType();
unsigned BitWidth = VT.getSizeInBits();
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (and x, undef) -> 0
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
@@ -1812,10 +1812,10 @@
if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
N0.getValueType(), N0Op0);
-
+
// Replace uses of the AND with uses of the Zero extend node.
CombineTo(N, Zext);
-
+
// We actually want to replace all uses of the any_extend with the
// zero_extend, to avoid duplicating things. This will later cause this
// AND to be folded.
@@ -1827,7 +1827,7 @@
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
-
+
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
LL.getValueType().isInteger()) {
// fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
@@ -1872,7 +1872,7 @@
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.getNode()) return Tmp;
}
-
+
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
if (!VT.isVector() &&
@@ -1921,7 +1921,7 @@
return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
-
+
// fold (and (load x), 255) -> (zextload x, i8)
// fold (and (extload x, i16), 255) -> (zextload x, i8)
if (N1C && N0.getOpcode() == ISD::LOAD) {
@@ -1969,7 +1969,7 @@
}
}
}
-
+
return SDValue();
}
@@ -1980,13 +1980,13 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N1.getValueType();
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (or x, undef) -> -1
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(~0ULL, VT);
@@ -2022,12 +2022,12 @@
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
-
+
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
LL.getValueType().isInteger()) {
// fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
// fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
- if (cast<ConstantSDNode>(LR)->isNullValue() &&
+ if (cast<ConstantSDNode>(LR)->isNullValue() &&
(Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
LR.getValueType(), LL, RL);
@@ -2036,7 +2036,7 @@
}
// fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
// fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
- if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
+ if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
(Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
LR.getValueType(), LL, RL);
@@ -2058,13 +2058,13 @@
LL, LR, Result);
}
}
-
+
// Simplify: (or (op x...), (op y...)) -> (op (or x, y))
if (N0.getOpcode() == N1.getOpcode()) {
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.getNode()) return Tmp;
}
-
+
// (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
if (N0.getOpcode() == ISD::AND &&
N1.getOpcode() == ISD::AND &&
@@ -2078,7 +2078,7 @@
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
const APInt &RHSMask =
cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
-
+
if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
@@ -2087,7 +2087,7 @@
DAG.getConstant(LHSMask | RHSMask, VT));
}
}
-
+
// See if this is some rotate idiom.
if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
return SDValue(Rot, 0);
@@ -2105,13 +2105,13 @@
return false;
}
}
-
+
if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
Shift = Op;
return true;
}
- return false;
+ return false;
}
// MatchRotate - Handle an 'or' of two operands. If this is one of the many
@@ -2137,13 +2137,13 @@
SDValue RHSMask; // AND value if any.
if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
return 0; // Not part of a rotate.
-
+
if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
return 0; // Not shifting the same value.
if (LHSShift.getOpcode() == RHSShift.getOpcode())
return 0; // Shifts must disagree.
-
+
// Canonicalize shl to left side in a shl/srl pair.
if (RHSShift.getOpcode() == ISD::SHL) {
std::swap(LHS, RHS);
@@ -2170,11 +2170,11 @@
Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
else
Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
-
+
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.getNode() || RHSMask.getNode()) {
APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
-
+
if (LHSMask.getNode()) {
APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
@@ -2183,23 +2183,23 @@
APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
}
-
+
Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
}
-
+
return Rot.getNode();
}
-
+
// If there is a mask here, and we have a variable shift, we can't be sure
// that we're masking out the right stuff.
if (LHSMask.getNode() || RHSMask.getNode())
return 0;
-
+
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
if (RHSShiftAmt.getOpcode() == ISD::SUB &&
LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
- if (ConstantSDNode *SUBC =
+ if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTL)
@@ -2211,12 +2211,12 @@
}
}
}
-
+
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
if (LHSShiftAmt.getOpcode() == ISD::SUB &&
RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
- if (ConstantSDNode *SUBC =
+ if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTR)
@@ -2256,7 +2256,7 @@
}
} else if (LExtOp0.getOpcode() == ISD::SUB &&
RExtOp0 == LExtOp0.getOperand(1)) {
- // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
+ // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
// (rotr x, y)
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
// (rotl x, (sub 32, y))
@@ -2270,7 +2270,7 @@
}
}
}
-
+
return 0;
}
@@ -2281,13 +2281,13 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (xor undef, undef) -> 0. This is a common idiom (misuse).
if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
return DAG.getConstant(0, VT);
@@ -2335,12 +2335,12 @@
N0.getNode()->hasOneUse() &&
isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
SDValue V = N0.getOperand(0);
- V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
+ V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
DAG.getConstant(1, V.getValueType()));
AddToWorkList(V.getNode());
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
}
-
+
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
@@ -2354,7 +2354,7 @@
}
}
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
- if (N1C && N1C->isAllOnesValue() &&
+ if (N1C && N1C->isAllOnesValue() &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
@@ -2390,18 +2390,18 @@
&Ops[0], Ops.size());
}
}
-
+
// Simplify: xor (op x...), (op y...) -> (op (xor x, y))
if (N0.getOpcode() == N1.getOpcode()) {
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
if (Tmp.getNode()) return Tmp;
}
-
+
// Simplify the expression using non-local knowledge.
if (!VT.isVector() &&
SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
+
return SDValue();
}
@@ -2410,13 +2410,13 @@
SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
SDNode *LHS = N->getOperand(0).getNode();
if (!LHS->hasOneUse()) return SDValue();
-
+
// We want to pull some binops through shifts, so that we have (and (shift))
// instead of (shift (and)), likewise for add, or, xor, etc. This sort of
// thing happens with address calculations, so it's important to canonicalize
// it.
bool HighBitSet = false; // Can we transform this if the high bit is set?
-
+
switch (LHS->getOpcode()) {
default: return SDValue();
case ISD::OR:
@@ -2427,12 +2427,12 @@
HighBitSet = true; // We can only transform sra if the high bit is set.
break;
case ISD::ADD:
- if (N->getOpcode() != ISD::SHL)
+ if (N->getOpcode() != ISD::SHL)
return SDValue(); // only shl(add) not sr[al](add).
HighBitSet = false; // We can only transform sra if the high bit is clear.
break;
}
-
+
// We require the RHS of the binop to be a constant as well.
ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
if (!BinOpCst) return SDValue();
@@ -2443,14 +2443,14 @@
// void foo(int *X, int i) { X[i & 1235] = 1; }
// int bar(int *X, int i) { return X[i & 255]; }
SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
- if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
+ if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
BinOpLHSVal->getOpcode() != ISD::SRA &&
BinOpLHSVal->getOpcode() != ISD::SRL) ||
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
return SDValue();
-
+
MVT VT = N->getValueType(0);
-
+
// If this is a signed shift right, and the high bit is modified by the
// logical operation, do not perform the transformation. The highBitSet
// boolean indicates the value of the high bit of the constant which would
@@ -2460,7 +2460,7 @@
if (BinOpRHSSignSet != HighBitSet)
return SDValue();
}
-
+
// Fold the constants, shifting the binop RHS by the shift amount.
SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
N->getValueType(0),
@@ -2481,7 +2481,7 @@
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
-
+
// fold (shl c1, c2) -> c1<<c2
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
@@ -2521,7 +2521,7 @@
return SDValue(N, 0);
// fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
- if (N1C && N0.getOpcode() == ISD::SHL &&
+ if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
@@ -2532,7 +2532,7 @@
}
// fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
// (srl (and x, (shl -1, c1)), (sub c1, c2))
- if (N1C && N0.getOpcode() == ISD::SRL &&
+ if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
@@ -2549,7 +2549,7 @@
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
-
+
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
}
@@ -2559,7 +2559,7 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
-
+
// fold (sra c1, c2) -> (sra c1, c2)
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
@@ -2597,8 +2597,8 @@
// fold (sra (shl X, m), (sub result_size, n))
// -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
- // result_size - n != m.
- // If truncate is free for the target sext(shl) is likely to result in better
+ // result_size - n != m.
+ // If truncate is free for the target sext(shl) is likely to result in better
// code.
if (N0.getOpcode() == ISD::SHL) {
// Get the two constanst of the shifts, CN0 = m, CN = n.
@@ -2611,8 +2611,8 @@
// Determine the residual right-shift amount.
unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
- // If the shift is not a no-op (in which case this should be just a sign
- // extend already), the truncated to type is legal, sign_extend is legal
+ // If the shift is not a no-op (in which case this should be just a sign
+ // extend already), the truncated to type is legal, sign_extend is legal
// on that type, and the the truncate to that type is both legal and free,
// perform the transform.
if (ShiftAmt &&
@@ -2630,7 +2630,7 @@
}
}
}
-
+
// fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND &&
@@ -2651,11 +2651,11 @@
}
}
- // Simplify, based on bits shifted out of the LHS.
+ // Simplify, based on bits shifted out of the LHS.
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
-
+
+
// If the sign bit is known to be zero, switch this to a SRL.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
@@ -2670,7 +2670,7 @@
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
-
+
// fold (srl c1, c2) -> c1 >>u c2
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
@@ -2687,9 +2687,9 @@
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(OpSizeInBits)))
return DAG.getConstant(0, VT);
-
+
// fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
- if (N1C && N0.getOpcode() == ISD::SRL &&
+ if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
@@ -2698,7 +2698,7 @@
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType()));
}
-
+
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
@@ -2711,30 +2711,30 @@
AddToWorkList(SmallShift.getNode());
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
}
-
+
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
// bit, which is unmodified by sra.
if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
if (N0.getOpcode() == ISD::SRA)
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
}
-
+
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
- if (N1C && N0.getOpcode() == ISD::CTLZ &&
+ if (N1C && N0.getOpcode() == ISD::CTLZ &&
N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
-
+
// If any of the input bits are KnownOne, then the input couldn't be all
// zeros, thus the result of the srl will always be zero.
if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
-
+
// If all of the bits input the to ctlz node are known to be zero, then
// the result of the ctlz is "32" and the result of the shift is one.
APInt UnknownBits = ~KnownZero & Mask;
if (UnknownBits == 0) return DAG.getConstant(1, VT);
-
+
// Otherwise, check to see if there is exactly one bit input to the ctlz.
if ((UnknownBits & (UnknownBits - 1)) == 0) {
// Okay, we know that only that the single bit specified by UnknownBits
@@ -2774,12 +2774,12 @@
DAG.getConstant(TruncC, TruncVT)));
}
}
-
+
// fold operands of srl based on knowledge that the low bits are not
// demanded.
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
+
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
}
@@ -2796,7 +2796,7 @@
SDValue DAGCombiner::visitCTTZ(SDNode *N) {
SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
-
+
// fold (cttz c1) -> c2
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
@@ -2806,7 +2806,7 @@
SDValue DAGCombiner::visitCTPOP(SDNode *N) {
SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
-
+
// fold (ctpop c1) -> c2
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
@@ -2875,7 +2875,7 @@
// fold (select X, Y, 0) -> (and X, Y)
if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
-
+
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N1, N2))
return SDValue(N, 0); // Don't revisit N.
@@ -2904,11 +2904,11 @@
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
-
+
// fold select_cc lhs, rhs, x, x, cc -> x
if (N2 == N3)
return N2;
-
+
// Determine if the condition we're dealing with is constant
SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
N0, N1, CC, N->getDebugLoc(), false);
@@ -2920,17 +2920,17 @@
else
return N3; // cond always false -> false val
}
-
+
// Fold to a simpler select_cc
if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
- return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
- SCC.getOperand(0), SCC.getOperand(1), N2, N3,
+ return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
+ SCC.getOperand(0), SCC.getOperand(1), N2, N3,
SCC.getOperand(2));
-
+
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N2, N3))
return SDValue(N, 0); // Don't revisit N.
-
+
// fold select_cc into other things, such as min/max/abs
return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
}
@@ -2944,7 +2944,7 @@
// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
// transformation. Returns true if extension are possible and the above
-// mentioned transformation is profitable.
+// mentioned transformation is profitable.
static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
unsigned ExtOpc,
SmallVector<SDNode*, 4> &ExtendNodes,
@@ -3017,13 +3017,13 @@
// fold (sext c1) -> c1
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
-
+
// fold (sext (sext x)) -> (sext x)
// fold (sext (aext x)) -> (sext x)
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
N0.getOperand(0));
-
+
if (N0.getOpcode() == ISD::TRUNCATE) {
// fold (sext (truncate (load x))) -> (sext (smaller load x))
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
@@ -3041,7 +3041,7 @@
unsigned MidBits = N0.getValueType().getSizeInBits();
unsigned DestBits = VT.getSizeInBits();
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
-
+
if (OpBits == DestBits) {
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
// bits, it is already ready.
@@ -3058,7 +3058,7 @@
if (NumSignBits > OpBits-MidBits)
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
}
-
+
// fold (sext (truncate x)) -> (sextinreg x).
if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
N0.getValueType())) {
@@ -3070,7 +3070,7 @@
DAG.getValueType(N0.getValueType()));
}
}
-
+
// fold (sext (load x)) -> (sext (truncate (sextload x)))
if (ISD::isNON_EXTLoad(N0.getNode()) &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -3137,21 +3137,21 @@
return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
-
+
// sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
if (N0.getOpcode() == ISD::SETCC) {
- SDValue SCC =
+ SDValue SCC =
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
if (SCC.getNode()) return SCC;
}
-
+
// fold (sext x) -> (zext x) if the sign bit is known zero.
if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
-
+
return SDValue();
}
@@ -3190,7 +3190,7 @@
}
return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
}
-
+
// fold (zext (and (trunc x), cst)) -> (and x, cst).
if (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
@@ -3206,7 +3206,7 @@
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
X, DAG.getConstant(Mask, VT));
}
-
+
// fold (zext (load x)) -> (zext (truncate (zextload x)))
if (ISD::isNON_EXTLoad(N0.getNode()) &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -3273,23 +3273,23 @@
return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
-
+
// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
- SDValue SCC =
+ SDValue SCC =
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
if (SCC.getNode()) return SCC;
}
-
+
return SDValue();
}
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
MVT VT = N->getValueType(0);
-
+
// fold (aext c1) -> c1
if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
@@ -3300,7 +3300,7 @@
N0.getOpcode() == ISD::ZERO_EXTEND ||
N0.getOpcode() == ISD::SIGN_EXTEND)
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
-
+
// fold (aext (truncate (load x))) -> (aext (smaller load x))
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
@@ -3321,7 +3321,7 @@
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
}
-
+
// fold (aext (and (trunc x), cst)) -> (and x, cst).
if (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
@@ -3337,7 +3337,7 @@
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
X, DAG.getConstant(Mask, VT));
}
-
+
// fold (aext (load x)) -> (aext (truncate (extload x)))
if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -3360,7 +3360,7 @@
ExtLoad.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
-
+
// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
// fold (aext (sextload x)) -> (aext (truncate (sextload x)))
// fold (aext ( extload x)) -> (aext (truncate (extload x)))
@@ -3381,17 +3381,17 @@
ExtLoad.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
-
+
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
- SDValue SCC =
+ SDValue SCC =
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
if (SCC.getNode())
return SCC;
}
-
+
return SDValue();
}
@@ -3422,7 +3422,7 @@
APInt NewMask = Mask << Amt;
SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
if (SimplifyLHS.getNode())
- return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
+ return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
SimplifyLHS, V.getOperand(1));
}
}
@@ -3519,15 +3519,15 @@
MVT EVT = cast<VTSDNode>(N1)->getVT();
unsigned VTBits = VT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
-
+
// fold (sext_in_reg c1) -> c1
if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
-
+
// If the input is already sign extended, just drop the extension.
if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
return N0;
-
+
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
@@ -3547,12 +3547,12 @@
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
-
+
// fold operands of sext_in_reg based on knowledge that the top bits are not
// demanded.
if (SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
+
// fold (sext_in_reg (load x)) -> (smaller sextload x)
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
SDValue NarrowLoad = ReduceLoadWidth(N);
@@ -3575,7 +3575,7 @@
}
// fold (sext_inreg (extload x)) -> (sextload x)
- if (ISD::isEXTLoad(N0.getNode()) &&
+ if (ISD::isEXTLoad(N0.getNode()) &&
ISD::isUNINDEXEDLoad(N0.getNode()) &&
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -3660,7 +3660,7 @@
}
/// CombineConsecutiveLoads - build_pair (load, load) -> load
-/// if load locations are consecutive.
+/// if load locations are consecutive.
SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
assert(N->getOpcode() == ISD::BUILD_PAIR);
@@ -3709,23 +3709,23 @@
if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
N0.getOperand(i).getOpcode() != ISD::Constant &&
N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
- isSimple = false;
+ isSimple = false;
break;
}
-
+
MVT DestEltVT = N->getValueType(0).getVectorElementType();
assert(!DestEltVT.isVector() &&
"Element type of vector ValueType must not be vector!");
if (isSimple)
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
}
-
+
// If the input is a constant, let getNode fold it.
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
if (Res.getNode() != N) return Res;
}
-
+
// (conv (conv x, t1), t2) -> (conv x, t2)
if (N0.getOpcode() == ISD::BIT_CONVERT)
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
@@ -3764,7 +3764,7 @@
SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
N0.getOperand(0));
AddToWorkList(NewConv.getNode());
-
+
APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
if (N0.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
@@ -3773,7 +3773,7 @@
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
NewConv, DAG.getConstant(~SignBit, VT));
}
-
+
// fold (bitconvert (fcopysign cst, x)) ->
// (or (and (bitconvert x), sign), (and cst, (not sign)))
// Note that we don't handle (copysign x, cst) because this can always be
@@ -3803,7 +3803,7 @@
X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
AddToWorkList(X.getNode());
}
-
+
APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
X, DAG.getConstant(SignBit, VT));
@@ -3819,13 +3819,13 @@
}
}
- // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
+ // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
if (N0.getOpcode() == ISD::BUILD_PAIR) {
SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
if (CombineLD.getNode())
return CombineLD;
}
-
+
return SDValue();
}
@@ -3835,18 +3835,18 @@
}
/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
-/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
+/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type.
SDValue DAGCombiner::
ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
MVT SrcEltVT = BV->getOperand(0).getValueType();
-
+
// If this is already the right type, we're done.
if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
-
+
unsigned SrcBitSize = SrcEltVT.getSizeInBits();
unsigned DstBitSize = DstEltVT.getSizeInBits();
-
+
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP<->INT cases.
if (SrcBitSize == DstBitSize) {
@@ -3861,7 +3861,7 @@
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
-
+
// Otherwise, we're growing or shrinking the elements. To avoid having to
// handle annoying details of growing/shrinking FP values, we convert them to
// int first.
@@ -3873,24 +3873,24 @@
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT;
}
-
+
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
if (DstEltVT.isFloatingPoint()) {
assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
-
+
// Next, convert to FP elements of the same size.
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
}
-
+
// Okay, we know the src/dst types are both integers of differing types.
// Handling growing first.
assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
if (SrcBitSize < DstBitSize) {
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
-
+
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e;
i += NumInputsPerOutput) {
@@ -3903,11 +3903,11 @@
SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
if (Op.getOpcode() == ISD::UNDEF) continue;
EltIsUndef = false;
-
+
NewBits |=
APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
}
-
+
if (EltIsUndef)
Ops.push_back(DAG.getUNDEF(DstEltVT));
else
@@ -3918,7 +3918,7 @@
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
-
+
// Finally, this must be the case where we are shrinking elements: each input
// turns into multiple outputs.
bool isS2V = ISD::isScalarToVector(BV);
@@ -3960,13 +3960,13 @@
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (fadd c1, c2) -> (fadd c1, c2)
if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
@@ -3984,14 +3984,14 @@
if (isNegatibleForFree(N0, LegalOperations) == 2)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
GetNegatedExpression(N0, DAG, LegalOperations));
-
+
// If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
N0.getOperand(1), N1));
-
+
return SDValue();
}
@@ -4001,13 +4001,13 @@
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT VT = N->getValueType(0);
-
+
// fold vector ops
if (VT.isVector()) {
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (fsub c1, c2) -> c1-c2
if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
@@ -4025,7 +4025,7 @@
if (isNegatibleForFree(N1, LegalOperations))
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
GetNegatedExpression(N1, DAG, LegalOperations));
-
+
return SDValue();
}
@@ -4041,7 +4041,7 @@
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (fmul c1, c2) -> c1*c2
if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
@@ -4058,7 +4058,7 @@
if (N1CFP && N1CFP->isExactlyValue(-1.0))
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
-
+
// fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
@@ -4070,14 +4070,14 @@
GetNegatedExpression(N1, DAG, LegalOperations));
}
}
-
+
// If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
- DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
+ DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
N0.getOperand(1), N1));
-
+
return SDValue();
}
@@ -4093,24 +4093,24 @@
SDValue FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.getNode()) return FoldedVOp;
}
-
+
// fold (fdiv c1, c2) -> c1/c2
if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
-
-
+
+
// (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
// Both can be negated for free, check to see if at least one is cheaper
// negated.
if (LHSNeg == 2 || RHSNeg == 2)
- return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
+ return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
GetNegatedExpression(N0, DAG, LegalOperations),
GetNegatedExpression(N1, DAG, LegalOperations));
}
}
-
+
return SDValue();
}
@@ -4137,7 +4137,7 @@
if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
-
+
if (N1CFP) {
const APFloat& V = N1CFP->getValueAPF();
// copysign(x, c1) -> fabs(x) iff ispos(c1)
@@ -4151,7 +4151,7 @@
DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
}
}
-
+
// copysign(fabs(x), y) -> copysign(x, y)
// copysign(fneg(x), y) -> copysign(x, y)
// copysign(copysign(x,z), y) -> copysign(x, y)
@@ -4163,18 +4163,18 @@
// copysign(x, abs(y)) -> abs(x)
if (N1.getOpcode() == ISD::FABS)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
-
+
// copysign(x, copysign(y,z)) -> copysign(x, z)
if (N1.getOpcode() == ISD::FCOPYSIGN)
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
N0, N1.getOperand(1));
-
+
// copysign(x, fp_extend(y)) -> copysign(x, y)
// copysign(x, fp_round(y)) -> copysign(x, y)
if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
N0, N1.getOperand(0));
-
+
return SDValue();
}
@@ -4187,12 +4187,12 @@
// fold (sint_to_fp c1) -> c1fp
if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
-
+
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
// but UINT_TO_FP is legal on this target, try to convert.
if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
- // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
+ // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
}
@@ -4209,16 +4209,16 @@
// fold (uint_to_fp c1) -> c1fp
if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
-
+
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
// but SINT_TO_FP is legal on this target, try to convert.
if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
- // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
+ // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
}
-
+
return SDValue();
}
@@ -4226,7 +4226,7 @@
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
-
+
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
@@ -4238,7 +4238,7 @@
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
-
+
// fold (fp_to_uint c1fp) -> c1
if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
@@ -4251,15 +4251,15 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
-
+
// fold (fp_round c1fp) -> c1fp
if (N0CFP && N0.getValueType() != MVT::ppcf128)
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
-
+
// fold (fp_round (fp_extend x)) -> x
if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
return N0.getOperand(0);
-
+
// fold (fp_round (fp_round x)) -> (fp_round x)
if (N0.getOpcode() == ISD::FP_ROUND) {
// This is a value preserving truncation if both round's are.
@@ -4268,7 +4268,7 @@
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getIntPtrConstant(IsTrunc));
}
-
+
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
@@ -4277,7 +4277,7 @@
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
Tmp, N0.getOperand(1));
}
-
+
return SDValue();
}
@@ -4286,7 +4286,7 @@
MVT VT = N->getValueType(0);
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
-
+
// fold (fp_round_inreg c1fp) -> c1fp
if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
@@ -4300,9 +4300,9 @@
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
-
+
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
- if (N->hasOneUse() &&
+ if (N->hasOneUse() &&
N->use_begin()->getOpcode() == ISD::FP_ROUND)
return SDValue();
@@ -4321,7 +4321,7 @@
In, N0.getOperand(1));
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
}
-
+
// fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
@@ -4365,7 +4365,7 @@
N->getValueType(0), Int);
}
}
-
+
return SDValue();
}
@@ -4373,7 +4373,7 @@
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
MVT VT = N->getValueType(0);
-
+
// fold (fabs c1) -> fabs(c1)
if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
@@ -4384,7 +4384,7 @@
// fold (fabs (fcopysign x, y)) -> (fabs x)
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
-
+
// Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
// constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
@@ -4393,14 +4393,14 @@
SDValue Int = N0.getOperand(0);
MVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
- Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
+ Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
N->getValueType(0), Int);
}
}
-
+
return SDValue();
}
@@ -4409,7 +4409,7 @@
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-
+
// never taken branch, fold to chain
if (N1C && N1C->isNullValue())
return Chain;
@@ -4418,7 +4418,7 @@
return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
- if (N1.getOpcode() == ISD::SETCC &&
+ if (N1.getOpcode() == ISD::SETCC &&
TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
Chain, N1.getOperand(2),
@@ -4433,7 +4433,7 @@
SDValue DAGCombiner::visitBR_CC(SDNode *N) {
CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
-
+
// Use SimplifySetCC to simplify SETCC's.
SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
@@ -4510,7 +4510,7 @@
if (isa<ConstantSDNode>(Offset) &&
cast<ConstantSDNode>(Offset)->isNullValue())
return false;
-
+
// Try turning it into a pre-indexed load / store except when:
// 1) The new base ptr is a frame index.
// 2) If N is a store and the new base ptr is either the same as or is a
@@ -4523,7 +4523,7 @@
// (plus the implicit offset) to a register to preinc anyway.
if (isa<FrameIndexSDNode>(BasePtr))
return false;
-
+
// Check #2.
if (!isLoad) {
SDValue Val = cast<StoreSDNode>(N)->getValue();
@@ -4621,7 +4621,7 @@
if (Ptr.getNode()->hasOneUse())
return false;
-
+
for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
E = Ptr.getNode()->use_end(); I != E; ++I) {
SDNode *Op = *I;
@@ -4729,13 +4729,13 @@
int64_t FrameOffset = 0;
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
FrameIdx = FI->getIndex();
- } else if (Ptr.getOpcode() == ISD::ADD &&
+ } else if (Ptr.getOpcode() == ISD::ADD &&
isa<ConstantSDNode>(Ptr.getOperand(1)) &&
isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
FrameOffset = Ptr.getConstantOperandVal(1);
}
-
+
if (FrameIdx != (1 << 31)) {
// FIXME: Handle FI+CST.
const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
@@ -4748,18 +4748,18 @@
// object is 16-byte aligned.
unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
unsigned Align = MinAlign(ObjectOffset, StackAlign);
-
+
// Finally, the frame object itself may have a known alignment. Factor
// the alignment + offset into a new alignment. For example, if we know
// the FI is 8 byte aligned, but the pointer is 4 off, we really have a
// 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
// offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
- unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
+ unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
FrameOffset);
return std::max(Align, FIInfoAlign);
}
}
-
+
return 0;
}
@@ -4767,7 +4767,7 @@
LoadSDNode *LD = cast<LoadSDNode>(N);
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
-
+
// Try to infer better alignment information than the load already has.
if (!Fast && LD->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
@@ -4826,7 +4826,7 @@
}
}
}
-
+
// If this load is directly stored, replace the load value with the stored
// value.
// TODO: Handle store large -> read small portion.
@@ -4840,11 +4840,11 @@
return CombineTo(N, Chain.getOperand(1), Chain);
}
}
-
+
if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
SDValue BetterChain = FindBetterChain(N, Chain);
-
+
// If there is a better chain.
if (Chain != BetterChain) {
SDValue ReplLoad;
@@ -4861,14 +4861,14 @@
BetterChain, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->getMemoryVT(),
- LD->isVolatile(),
+ LD->isVolatile(),
LD->getAlignment());
}
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
MVT::Other, Chain, ReplLoad.getValue(1));
-
+
// Replace uses with load result and token factor. Don't add users
// to work list.
return CombineTo(N, ReplLoad.getValue(0), Token, false);
@@ -4887,7 +4887,7 @@
SDValue Chain = ST->getChain();
SDValue Value = ST->getValue();
SDValue Ptr = ST->getBasePtr();
-
+
// Try to infer better alignment information than the store already has.
if (!Fast && ST->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
@@ -4985,10 +4985,10 @@
}
}
- if (CombinerAA) {
+ if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
SDValue BetterChain = FindBetterChain(N, Chain);
-
+
// If there is a better chain.
if (Chain != BetterChain) {
// Replace the chain to avoid dependency.
@@ -5003,7 +5003,7 @@
ST->getSrcValue(), ST->getSrcValueOffset(),
ST->isVolatile(), ST->getAlignment());
}
-
+
// Create token to keep both nodes around.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
MVT::Other, Chain, ReplStore);
@@ -5012,7 +5012,7 @@
return CombineTo(N, Token, false);
}
}
-
+
// Try transforming N to an indexed store.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
return SDValue(N, 0);
@@ -5023,7 +5023,7 @@
// See if we can simplify the input to this truncstore with knowledge that
// only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
- SDValue Shorter =
+ SDValue Shorter =
GetDemandedBits(Value,
APInt::getLowBitsSet(Value.getValueSizeInBits(),
ST->getMemoryVT().getSizeInBits()));
@@ -5033,7 +5033,7 @@
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->getMemoryVT(),
ST->isVolatile(), ST->getAlignment());
-
+
// Otherwise, see if we can simplify the operation with
// SimplifyDemandedBits, which only works if the value has a single use.
if (SimplifyDemandedBits(Value,
@@ -5042,7 +5042,7 @@
ST->getMemoryVT().getSizeInBits())))
return SDValue(N, 0);
}
-
+
// If this is a load followed by a store to the same location, then the store
// is dead/noop.
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
@@ -5075,7 +5075,7 @@
SDValue InVec = N->getOperand(0);
SDValue InVal = N->getOperand(1);
SDValue EltNo = N->getOperand(2);
-
+
// If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
// vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
@@ -5087,7 +5087,7 @@
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
InVec.getValueType(), &Ops[0], Ops.size());
}
-
+
return SDValue();
}
@@ -5137,7 +5137,7 @@
// (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
// =>
// (load $addr+1*size)
-
+
// If the bit convert changed the number of elements, it is unsafe
// to examine the mask.
if (BCNumEltsChanged)
@@ -5201,7 +5201,7 @@
for (unsigned i = 0; i != NumInScalars; ++i) {
// Ignore undef inputs.
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-
+
// If this input is something other than a EXTRACT_VECTOR_ELT with a
// constant index, bail out.
if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
@@ -5209,7 +5209,7 @@
VecIn1 = VecIn2 = SDValue(0, 0);
break;
}
-
+
// If the input vector type disagrees with the result of the build_vector,
// we can't make a shuffle.
SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
@@ -5217,11 +5217,11 @@
VecIn1 = VecIn2 = SDValue(0, 0);
break;
}
-
+
// Otherwise, remember this. We allow up to two distinct input vectors.
if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
continue;
-
+
if (VecIn1.getNode() == 0) {
VecIn1 = ExtractedFromVec;
} else if (VecIn2.getNode() == 0) {
@@ -5232,7 +5232,7 @@
break;
}
}
-
+
// If everything is good, we can make a shuffle operation.
if (VecIn1.getNode()) {
SmallVector<SDValue, 8> BuildVecIndices;
@@ -5241,9 +5241,9 @@
BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy()));
continue;
}
-
+
SDValue Extract = N->getOperand(i);
-
+
// If extracting from the first vector, just use the index directly.
if (Extract.getOperand(0) == VecIn1) {
BuildVecIndices.push_back(Extract.getOperand(1));
@@ -5255,7 +5255,7 @@
cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
}
-
+
// Add count and size info.
MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
@@ -5279,7 +5279,7 @@
&BuildVecIndices[0], BuildVecIndices.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
}
-
+
return SDValue();
}
@@ -5411,7 +5411,7 @@
NumElts) {
MappedOps.push_back(ShufMask.getOperand(i));
} else {
- unsigned NewIdx =
+ unsigned NewIdx =
cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
NumElts;
MappedOps.push_back(DAG.getConstant(NewIdx,
@@ -5428,7 +5428,7 @@
DAG.getUNDEF(N->getValueType(0)),
ShufMask);
}
-
+
return SDValue();
}
@@ -5507,7 +5507,7 @@
// If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
// this operation.
- if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
+ if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
RHS.getOpcode() == ISD::BUILD_VECTOR) {
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
@@ -5540,21 +5540,21 @@
Ops.back().getOpcode() == ISD::ConstantFP) &&
"Scalar binop didn't fold!");
}
-
+
if (Ops.size() == LHS.getNumOperands()) {
MVT VT = LHS.getValueType();
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
}
-
+
return SDValue();
}
SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
SDValue N1, SDValue N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
-
+
SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
cast<CondCodeSDNode>(N0.getOperand(2))->get());
@@ -5567,7 +5567,7 @@
if (SCC.getOpcode() == ISD::SELECT_CC) {
SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
N0.getValueType(),
- SCC.getOperand(0), SCC.getOperand(1),
+ SCC.getOperand(0), SCC.getOperand(1),
SCC.getOperand(4));
AddToWorkList(SETCC.getNode());
return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
@@ -5585,9 +5585,9 @@
/// returns true. As such, they should return the appropriate thing (e.g. the
/// node) back to the top-level of the DAG combiner loop to avoid it being
/// looked at.
-bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
+bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
SDValue RHS) {
-
+
// If this is a select from two identical things, try to pull the operation
// through the select.
if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
@@ -5630,21 +5630,21 @@
Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
LLD->getBasePtr().getValueType(),
TheSelect->getOperand(0),
- TheSelect->getOperand(1),
+ TheSelect->getOperand(1),
LLD->getBasePtr(), RLD->getBasePtr(),
TheSelect->getOperand(4));
}
}
-
+
if (Addr.getNode()) {
SDValue Load;
if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
Load = DAG.getLoad(TheSelect->getValueType(0),
TheSelect->getDebugLoc(),
LLD->getChain(),
- Addr,LLD->getSrcValue(),
+ Addr,LLD->getSrcValue(),
LLD->getSrcValueOffset(),
- LLD->isVolatile(),
+ LLD->isVolatile(),
LLD->getAlignment());
} else {
Load = DAG.getExtLoad(LLD->getExtensionType(),
@@ -5653,13 +5653,13 @@
LLD->getChain(), Addr, LLD->getSrcValue(),
LLD->getSrcValueOffset(),
LLD->getMemoryVT(),
- LLD->isVolatile(),
+ LLD->isVolatile(),
LLD->getAlignment());
}
// Users of the select now use the result of the load.
CombineTo(TheSelect, Load);
-
+
// Users of the old loads now use the new load's chain. We know the
// old-load value is dead now.
CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
@@ -5669,11 +5669,11 @@
}
}
}
-
+
return false;
}
-SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
+SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
SDValue N2, SDValue N3,
ISD::CondCode CC, bool NotExtCompare) {
MVT VT = N2.getValueType();
@@ -5693,7 +5693,7 @@
// fold select_cc false, x, y -> y
if (SCCC && SCCC->isNullValue())
return N3;
-
+
// Check to see if we can simplify the select into an fabs node
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
// Allow either -0.0 or 0.0
@@ -5703,7 +5703,7 @@
N0 == N2 && N3.getOpcode() == ISD::FNEG &&
N2 == N3.getOperand(0))
return DAG.getNode(ISD::FABS, DL, VT, N0);
-
+
// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
N0 == N3 && N2.getOpcode() == ISD::FNEG &&
@@ -5711,7 +5711,7 @@
return DAG.getNode(ISD::FABS, DL, VT, N3);
}
}
-
+
// Check to see if we can perform the "gzip trick", transforming
// (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
@@ -5754,16 +5754,16 @@
return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
}
}
-
+
// fold select C, 16, 0 -> shl C, 4
if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
-
+
// If the caller doesn't want us to simplify this into a zext of a compare,
// don't do it.
if (NotExtCompare && N2C->getAPIntValue() == 1)
return SDValue();
-
+
// Get a SetCC of the condition
// FIXME: Should probably make sure that setcc is legal if we ever have a
// target where it isn't.
@@ -5785,7 +5785,7 @@
AddToWorkList(SCC.getNode());
AddToWorkList(Temp.getNode());
-
+
if (N2C->getAPIntValue() == 1)
return Temp;
@@ -5794,7 +5794,7 @@
DAG.getConstant(N2C->getAPIntValue().logBase2(),
getShiftAmountTy()));
}
-
+
// Check to see if this is the equivalent of setcc
// FIXME: Turn all of these into setcc if setcc if setcc is legal
// otherwise, go ahead with the folds.
@@ -5807,18 +5807,18 @@
Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
return Res;
}
-
+
// fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
- if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
+ if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
(!LegalOperations ||
TLI.isOperationLegal(ISD::CTLZ, XType))) {
SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
- return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
+ return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
DAG.getConstant(Log2_32(XType.getSizeInBits()),
getShiftAmountTy()));
}
// fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
- if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
+ if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
XType, DAG.getConstant(0, XType), N0);
SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
@@ -5835,7 +5835,7 @@
return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
}
}
-
+
// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
@@ -5870,7 +5870,7 @@
}
}
}
-
+
return SDValue();
}
@@ -5878,7 +5878,7 @@
SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans) {
- TargetLowering::DAGCombinerInfo
+ TargetLowering::DAGCombinerInfo
DagCombineInfo(DAG, Level == Unrestricted, false, this);
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
}
@@ -5916,7 +5916,7 @@
static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
// Assume it is a primitive operation.
Base = Ptr; Offset = 0;
-
+
// If it's an adding a simple constant then integrate the offset.
if (Base.getOpcode() == ISD::ADD) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
@@ -5924,7 +5924,7 @@
Offset += C->getZExtValue();
}
}
-
+
// If it's any of the following then it can't alias with anything but itself.
return isa<FrameIndexSDNode>(Base) ||
isa<ConstantPoolSDNode>(Base) ||
@@ -5939,18 +5939,18 @@
const Value *SrcValue2, int SrcValueOffset2) const {
// If they are the same then they must be aliases.
if (Ptr1 == Ptr2) return true;
-
+
// Gather base node and offset information.
SDValue Base1, Base2;
int64_t Offset1, Offset2;
bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
-
+
// If they have a same base address then...
if (Base1 == Base2)
// Check to see if the addresses overlap.
return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
-
+
// If we know both bases then they can't alias.
if (KnownBase1 && KnownBase2) return false;
@@ -5959,7 +5959,7 @@
int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
- AliasAnalysis::AliasResult AAResult =
+ AliasAnalysis::AliasResult AAResult =
AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
if (AAResult == AliasAnalysis::NoAlias)
return false;
@@ -5988,7 +5988,7 @@
} else {
assert(0 && "FindAliasInfo expected a memory operand");
}
-
+
return false;
}
@@ -5998,7 +5998,7 @@
SmallVector<SDValue, 8> &Aliases) {
SmallVector<SDValue, 8> Chains; // List of chains to visit.
std::set<SDNode *> Visited; // Visited node set.
-
+
// Get alias information for node.
SDValue Ptr;
int64_t Size;
@@ -6008,23 +6008,23 @@
// Starting off.
Chains.push_back(OriginalChain);
-
+
// Look at each chain and determine if it is an alias. If so, add it to the
// aliases list. If not, then continue up the chain looking for the next
- // candidate.
+ // candidate.
while (!Chains.empty()) {
SDValue Chain = Chains.back();
Chains.pop_back();
-
+
// Don't bother if we've been before.
if (Visited.find(Chain.getNode()) != Visited.end()) continue;
Visited.insert(Chain.getNode());
-
+
switch (Chain.getOpcode()) {
case ISD::EntryToken:
// Entry token is ideal chain operand, but handled in FindBetterChain.
break;
-
+
case ISD::LOAD:
case ISD::STORE: {
// Get alias information for Chain.
@@ -6034,7 +6034,7 @@
int OpSrcValueOffset;
bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
OpSrcValue, OpSrcValueOffset);
-
+
// If chain is alias then stop here.
if (!(IsLoad && IsOpLoad) &&
isAlias(Ptr, Size, SrcValue, SrcValueOffset,
@@ -6042,13 +6042,13 @@
Aliases.push_back(Chain);
} else {
// Look further up the chain.
- Chains.push_back(Chain.getOperand(0));
+ Chains.push_back(Chain.getOperand(0));
// Clean up old chain.
AddToWorkList(Chain.getNode());
}
break;
}
-
+
case ISD::TokenFactor:
// We have to check each of the operands of the token factor, so we queue
// then up. Adding the operands to the queue (stack) in reverse order
@@ -6059,7 +6059,7 @@
// Eliminate the token factor if we can.
AddToWorkList(Chain.getNode());
break;
-
+
default:
// For all other instructions we will just have to take what we can get.
Aliases.push_back(Chain);
@@ -6072,10 +6072,10 @@
/// for a better chain (aliasing node.)
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
-
+
// Accumulate all the aliases to this node.
GatherAllAliases(N, OldChain, Aliases);
-
+
if (Aliases.size() == 0) {
// If no operands then chain to entry token.
return DAG.getEntryNode();
@@ -6090,7 +6090,7 @@
// Make sure the old chain gets cleaned up.
if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
-
+
return NewChain;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Feb 17 16:15:04 2009
@@ -58,17 +58,17 @@
bool TypesNeedLegalizing;
// Libcall insertion helpers.
-
+
/// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
/// legalized. We use this to ensure that calls are properly serialized
/// against each other, including inserted libcalls.
SDValue LastCALLSEQ_END;
-
+
/// IsLegalizingCall - This member is used *only* for purposes of providing
- /// helpful assertions that a libcall isn't created while another call is
+ /// helpful assertions that a libcall isn't created while another call is
/// being legalized (which could lead to non-serialized call sequences).
bool IsLegalizingCall;
-
+
/// IsLegalizingCallArguments - This member is used only for the purpose
/// of providing assert to check for LegalizeTypes because legalizing an
/// operation might introduce call nodes that might need type legalization.
@@ -79,7 +79,7 @@
Promote, // This operation should be executed in a larger type.
Expand // Try to expand this to other ops, otherwise use a libcall.
};
-
+
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
@@ -104,12 +104,12 @@
/// which operands are the split version of the input. This allows us
/// to avoid splitting the same node more than once.
std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
-
+
/// ScalarizedNodes - For nodes that need to be converted from vector types to
/// scalar types, this contains the mapping of ones we have already
/// processed to the result.
std::map<SDValue, SDValue> ScalarizedNodes;
-
+
/// WidenNodes - For nodes that need to be widened from one vector type to
/// another, this contains the mapping of those that we have already widen.
/// This allows us to avoid widening more than once.
@@ -158,18 +158,18 @@
/// HandleOp - Legalize, Promote, or Expand the specified operand as
/// appropriate for its type.
void HandleOp(SDValue Op);
-
+
/// LegalizeOp - We know that the specified value has a legal type.
/// Recursively ensure that the operands have legal types, then return the
/// result.
SDValue LegalizeOp(SDValue O);
-
+
/// UnrollVectorOp - We know that the given vector has a legal type, however
/// the operation it performs is not legal and is an operation that we have
/// no way of lowering. "Unroll" the vector, splitting out the scalars and
/// operating on each element individually.
SDValue UnrollVectorOp(SDValue O);
-
+
/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
/// is necessary to spill the vector being inserted into to memory, perform
@@ -192,7 +192,7 @@
/// types.
void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
- /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
+ /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
/// (e.g., v3i32 to v4i32). The produced value will have the correct value
/// for the existing elements but no guarantee is made about the new elements
/// at the end of the vector: it may be zero, ones, or garbage. This is useful
@@ -203,15 +203,15 @@
/// SplitVectorOp - Given an operand of vector type, break it down into
/// two smaller values.
void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
-
+
/// ScalarizeVectorOp - Given an operand of single-element vector type
/// (e.g. v1f32), convert it into the equivalent operation that returns a
/// scalar (e.g. f32) value.
SDValue ScalarizeVectorOp(SDValue O);
-
+
/// Useful 16 element vector type that is used to pass operands for widening.
- typedef SmallVector<SDValue, 16> SDValueVector;
-
+ typedef SmallVector<SDValue, 16> SDValueVector;
+
/// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
/// the LdChain contains a single load and false if it contains a token
/// factor for multiple loads. It takes
@@ -219,9 +219,9 @@
/// LdChain: location to return the load chain
/// Op: load operation to widen
/// NVT: widen vector result type we want for the load
- bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
+ bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
SDValue Op, MVT NVT);
-
+
/// Helper genWidenVectorLoads - Helper function to generate a set of
/// loads to load a vector with a resulting wider type. It takes
/// LdChain: list of chains for the load we have generated
@@ -231,22 +231,22 @@
/// SVOffset: memory disambiugation offset
/// Alignment: alignment of the memory
/// isVolatile: volatile load
- /// LdWidth: width of memory that we want to load
+ /// LdWidth: width of memory that we want to load
/// ResType: the wider result result type for the resulting loaded vector
SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, unsigned LdWidth,
MVT ResType, DebugLoc dl);
-
+
/// StoreWidenVectorOp - Stores a widen vector into non widen memory
/// location. It takes
/// ST: store node that we want to replace
/// Chain: incoming store chain
/// BasePtr: base address of where we want to store into
- SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
+ SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
SDValue BasePtr);
-
+
/// Helper genWidenVectorStores - Helper function to generate a set of
/// stores to store a widen vector into non widen memory
// It takes
@@ -257,14 +257,14 @@
// SVOffset: memory disambiugation offset
// Alignment: alignment of the memory
// isVolatile: volatile lod
- // ValOp: value to store
- // StWidth: width of memory that we want to store
+ // ValOp: value to store
+ // StWidth: width of memory that we want to store
void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, SDValue ValOp,
unsigned StWidth, DebugLoc dl);
-
+
/// isShuffleLegal - Return non-null if a vector shuffle is legal with the
/// specified mask and type. Targets can specify exactly which masks they
/// support and the code generator is tasked with not creating illegal masks.
@@ -275,7 +275,7 @@
/// If this is a legal shuffle, this method returns the (possibly promoted)
/// build_vector Mask. If it's not a legal shuffle, it returns null.
SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
-
+
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
@@ -288,7 +288,7 @@
LegalizeSetCCOperands(LHS, RHS, CC, dl);
LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
}
-
+
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
SDValue &Hi);
SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
@@ -296,7 +296,7 @@
SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
SDValue ExpandBUILD_VECTOR(SDNode *Node);
SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
- SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
+ SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
SDValue Op, DebugLoc dl);
SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
DebugLoc dl);
@@ -410,7 +410,7 @@
return Node;
if (Node->use_empty())
return 0; // No CallSeqEnd
-
+
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
if (TheChain.getValueType() != MVT::Other) {
@@ -423,16 +423,16 @@
TheChain = SDValue(Node, i);
break;
}
-
- // Otherwise, we walked into a node without a chain.
+
+ // Otherwise, we walked into a node without a chain.
if (TheChain.getValueType() != MVT::Other)
return 0;
}
}
-
+
for (SDNode::use_iterator UI = Node->use_begin(),
E = Node->use_end(); UI != E; ++UI) {
-
+
// Make sure to only follow users of our token chain.
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
@@ -443,19 +443,19 @@
return 0;
}
-/// FindCallStartFromCallEnd - Given a chained node that is part of a call
+/// FindCallStartFromCallEnd - Given a chained node that is part of a call
/// sequence, find the CALLSEQ_START node that initiates the call sequence.
static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
-
+
assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
-/// see if any uses can reach Dest. If no dest operands can get to dest,
+/// see if any uses can reach Dest. If no dest operands can get to dest,
/// legalize them, legalize ourself, and return false, otherwise, return true.
///
/// Keep track of the nodes we fine that actually do lead to Dest in
@@ -464,15 +464,15 @@
bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
if (N == Dest) return true; // N certainly leads to Dest :)
-
+
// If we've already processed this node and it does lead to Dest, there is no
// need to reprocess it.
if (NodesLeadingTo.count(N)) return true;
-
+
// If the first result of this node has been already legalized, then it cannot
// reach N.
switch (getTypeAction(N->getValueType(0))) {
- case Legal:
+ case Legal:
if (LegalizedNodes.count(SDValue(N, 0))) return false;
break;
case Promote:
@@ -482,7 +482,7 @@
if (ExpandedNodes.count(SDValue(N, 0))) return false;
break;
}
-
+
// Okay, this node has not already been legalized. Check and legalize all
// operands. If none lead to Dest, then we can legalize this node.
bool OperandsLeadToDest = false;
@@ -619,7 +619,7 @@
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
- SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
+ SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
Node->getOperand(1));
SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types.
@@ -682,7 +682,7 @@
SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
// Perform the original store, only redirected to the stack slot.
- SDValue Store = DAG.getTruncStore(Chain, dl,
+ SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, NULL, 0,StoredVT);
SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
SmallVector<SDValue, 8> Stores;
@@ -841,7 +841,7 @@
MVT NewLoadedVT;
NewLoadedVT = MVT::getIntegerVT(NumBits/2);
NumBits >>= 1;
-
+
unsigned Alignment = LD->getAlignment();
unsigned IncrementSize = NumBits / 8;
ISD::LoadExtType HiExtType = LD->getExtensionType();
@@ -958,7 +958,7 @@
SDValue Tmp1 = Vec;
SDValue Tmp2 = Val;
SDValue Tmp3 = Idx;
-
+
// If the target doesn't support this, we have to spill the input vector
// to a temporary stack slot, update the element, then reload it. This is
// badness. We could also load the value into a vector register (either
@@ -1000,7 +1000,7 @@
SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
return Op;
-
+
assert(isTypeLegal(Op.getValueType()) &&
"Caller should expand or promote operands that are not legal!");
SDNode *Node = Op.getNode();
@@ -1026,7 +1026,7 @@
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
SDValue Result = Op;
bool isCustom = false;
-
+
switch (Node->getOpcode()) {
case ISD::FrameIndex:
case ISD::EntryToken:
@@ -1090,7 +1090,7 @@
// The only option for these nodes is to custom lower them. If the target
// does not custom lower them, then return zero.
Tmp1 = TLI.LowerOperation(Op, DAG);
- if (Tmp1.getNode())
+ if (Tmp1.getNode())
Result = Tmp1;
else
Result = DAG.getConstant(0, TLI.getPointerTy());
@@ -1239,7 +1239,7 @@
}
break;
}
-
+
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN:
case ISD::INTRINSIC_VOID: {
@@ -1247,9 +1247,9 @@
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node->getOperand(i)));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
-
+
// Allow the target to custom lower its intrinsics if it wants to.
- if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
+ if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
TargetLowering::Custom) {
Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.getNode()) Result = Tmp3;
@@ -1261,17 +1261,17 @@
assert(Result.getNode()->getNumValues() == 2 &&
"Cannot return more than two values!");
- // Since loads produce two values, make sure to remember that we
+ // Since loads produce two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.getResNo());
- }
+ }
case ISD::DBG_STOPPOINT:
assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
-
+
switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
@@ -1280,14 +1280,14 @@
bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
MVT::Other);
bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
-
+
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
CU.getFilename());
-
+
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
@@ -1350,8 +1350,8 @@
Result = LegalizeOp(Node->getOperand(0));
break;
}
- break;
-
+ break;
+
case ISD::DEBUG_LOC:
assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
@@ -1374,7 +1374,7 @@
break;
}
}
- break;
+ break;
case ISD::DBG_LABEL:
case ISD::EH_LABEL:
@@ -1439,7 +1439,7 @@
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
@@ -1551,7 +1551,7 @@
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
break;
-
+
case ISD::FORMAL_ARGUMENTS:
case ISD::CALL:
// The only option for this is to custom lower it.
@@ -1572,7 +1572,7 @@
Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
MVT::Flag)) &&
"Lowering call/formal_arguments produced unexpected # results!");
-
+
// Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
// remember that we legalized all of them, so it doesn't get relegalized.
for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
@@ -1594,13 +1594,13 @@
break;
case ISD::INSERT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
- Tmp2 = LegalizeOp(Node->getOperand(1));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
assert(idx && "Operand must be a constant");
Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
}
- break;
+ break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
@@ -1629,13 +1629,13 @@
case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
case Expand:
// FIXME: An alternative would be to check to see if the target is not
- // going to custom lower this operation, we could bitcast to half elt
+ // going to custom lower this operation, we could bitcast to half elt
// width and perform two inserts at that width, if that is legal.
Tmp2 = Node->getOperand(1);
break;
}
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
@@ -1656,16 +1656,16 @@
if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
// SCALAR_TO_VECTOR requires that the type of the value being inserted
// match the element type of the vector being created.
- if (Tmp2.getValueType() ==
+ if (Tmp2.getValueType() ==
Op.getValueType().getVectorElementType()) {
SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Tmp1.getValueType(), Tmp2);
-
+
unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
MVT ShufMaskVT =
MVT::getIntVectorWithNumElements(NumElts);
MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
-
+
// We generate a shuffle of InVec and ScVec, so the shuffle mask
// should be 0,1,2,3,4,5... with the appropriate element replaced with
// elt 0 of the RHS.
@@ -1678,7 +1678,7 @@
}
SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
&ShufOps[0], ShufOps.size());
-
+
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
Tmp1, ScVec, ShufMask);
Result = LegalizeOp(Result);
@@ -1695,7 +1695,7 @@
Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
break;
}
-
+
Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
Result = DAG.UpdateNodeOperands(Result, Tmp1);
switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
@@ -1767,7 +1767,7 @@
// Cast the two input vectors.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
-
+
// Convert the shuffle mask to the right # elements.
Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
assert(Tmp3.getNode() && "Shuffle not legal?");
@@ -1777,7 +1777,7 @@
}
}
break;
-
+
case ISD::EXTRACT_VECTOR_ELT:
Tmp1 = Node->getOperand(0);
Tmp2 = LegalizeOp(Node->getOperand(1));
@@ -1785,13 +1785,13 @@
Result = ExpandEXTRACT_VECTOR_ELT(Result);
break;
- case ISD::EXTRACT_SUBVECTOR:
+ case ISD::EXTRACT_SUBVECTOR:
Tmp1 = Node->getOperand(0);
Tmp2 = LegalizeOp(Node->getOperand(1));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
Result = ExpandEXTRACT_SUBVECTOR(Result);
break;
-
+
case ISD::CONCAT_VECTORS: {
// Use extract/insert/build vector for now. We might try to be
// more clever later.
@@ -1814,7 +1814,7 @@
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);
-
+
// Recursively Legalize all of the inputs of the call end that do not lead
// to this call start. This ensures that any libcalls that need be inserted
// are inserted *before* the CALLSEQ_START.
@@ -1833,32 +1833,32 @@
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
-
+
// Do not try to legalize the target-specific arguments (#1+).
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
-
+
// Remember that the CALLSEQ_START is legalized.
AddLegalizedOperand(Op.getValue(0), Result);
if (Node->getNumValues() == 2) // If this has a flag result, remember it.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-
+
// Now that the callseq_start and all of the non-call nodes above this call
- // sequence have been legalized, legalize the call itself. During this
+ // sequence have been legalized, legalize the call itself. During this
// process, no libcalls can/will be inserted, guaranteeing that no calls
// can overlap.
assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
// Note that we are selecting this call!
LastCALLSEQ_END = SDValue(CallEnd, 0);
IsLegalizingCall = true;
-
+
// Legalize the call, starting from the CALLSEQ_END.
LegalizeOp(LastCALLSEQ_END);
assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
@@ -1874,8 +1874,8 @@
"Legalizing the call start should have legalized this node!");
return I->second;
}
-
- // Otherwise, the call start has been legalized and everything is going
+
+ // Otherwise, the call start has been legalized and everything is going
// according to plan. Just legalize ourselves normally here.
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
@@ -1899,7 +1899,7 @@
assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
// This finishes up call legalization.
IsLegalizingCall = false;
-
+
// If the CALLSEQ_END node has a flag, remember that we legalized it.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
if (Node->getNumValues() == 2)
@@ -1988,10 +1988,10 @@
Changed |= Op != Ops.back();
Ops.back() = Op;
}
-
+
if (Changed)
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
-
+
// INLINE asm returns a chain and flag, make sure to add both to the map.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
@@ -2003,7 +2003,7 @@
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
break;
case ISD::BRIND:
@@ -2012,7 +2012,7 @@
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
switch (getTypeAction(Node->getOperand(1).getValueType())) {
default: assert(0 && "Indirect target must be legal type (pointer)!");
case Legal:
@@ -2031,7 +2031,7 @@
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
- switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
+ switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
@@ -2046,7 +2046,7 @@
MVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
- Index= DAG.getNode(ISD::MUL, dl, PTy,
+ Index= DAG.getNode(ISD::MUL, dl, PTy,
Index, DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
@@ -2079,11 +2079,11 @@
break;
case Promote: {
Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
-
+
// The top bits of the promoted condition are not necessarily zero, ensure
// that the value is properly zero extended.
unsigned BitWidth = Tmp2.getValueSizeInBits();
- if (!DAG.MaskedValueIsZero(Tmp2,
+ if (!DAG.MaskedValueIsZero(Tmp2,
APInt::getHighBitsSet(BitWidth, BitWidth-1)))
Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
break;
@@ -2092,8 +2092,8 @@
// Basic block destination (Op#2) is always legal.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
-
- switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
+
+ switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
@@ -2104,12 +2104,12 @@
// Expand brcond's setcc into its constituent parts and create a BR_CC
// Node.
if (Tmp2.getOpcode() == ISD::SETCC) {
- Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
+ Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
+ Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
@@ -2122,11 +2122,11 @@
// Ensure that libcalls are emitted before a branch.
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
- Tmp2 = Node->getOperand(2); // LHS
+ Tmp2 = Node->getOperand(2); // LHS
Tmp3 = Node->getOperand(3); // RHS
Tmp4 = Node->getOperand(1); // CC
- LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
Tmp2, Tmp3, Tmp4, dl);
LastCALLSEQ_END = DAG.getEntryNode();
@@ -2137,10 +2137,10 @@
Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
Tmp4 = DAG.getCondCode(ISD::SETNE);
}
-
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
+
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
Node->getOperand(4));
-
+
switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
default: assert(0 && "Unexpected action for BR_CC!");
case TargetLowering::Legal: break;
@@ -2161,7 +2161,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
Tmp3 = Result.getValue(0);
Tmp4 = Result.getValue(1);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
@@ -2201,7 +2201,7 @@
break;
}
}
- // Since loads produce two values, make sure to remember that we
+ // Since loads produce two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp3);
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
@@ -2243,12 +2243,12 @@
if (ExtType == ISD::SEXTLOAD)
// Having the top bits zero doesn't help when sign extending.
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
Result.getValueType(),
Result, DAG.getValueType(SrcVT));
else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
// All the top bits are guaranteed to be zero - inform the optimizers.
- Result = DAG.getNode(ISD::AssertZext, dl,
+ Result = DAG.getNode(ISD::AssertZext, dl,
Result.getValueType(), Result,
DAG.getValueType(SrcVT));
@@ -2309,7 +2309,7 @@
IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
Node->getValueType(0), Tmp1, Tmp2,
LD->getSrcValue(), SVOffset + IncrementSize,
ExtraVT, isVolatile,
@@ -2370,7 +2370,7 @@
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
- Result = DAG.getNode(ISD::FP_EXTEND, dl,
+ Result = DAG.getNode(ISD::FP_EXTEND, dl,
Node->getValueType(0), Load);
Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
Tmp2 = LegalizeOp(Load.getValue(1));
@@ -2416,7 +2416,7 @@
Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
} else {
// 0 -> Lo
- Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
+ Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
Node->getOperand(0));
}
break;
@@ -2450,7 +2450,7 @@
} else {
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
}
-
+
// Since this produces two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
@@ -2466,7 +2466,7 @@
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
switch (Node->getNumOperands()) {
case 3: // ret val
Tmp2 = Node->getOperand(1);
@@ -2483,9 +2483,9 @@
// Big endian systems want the hi reg first.
if (TLI.isBigEndian())
std::swap(Lo, Hi);
-
+
if (Hi.getNode())
- Result = DAG.getNode(ISD::RET, dl, MVT::Other,
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other,
Tmp1, Lo, Tmp3, Hi,Tmp3);
else
Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
@@ -2495,7 +2495,7 @@
int InIx = Tmp2.getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
+
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
MVT TVT = MVT::getVectorVT(EVT, NumElems);
@@ -2508,10 +2508,10 @@
Tmp2 = ScalarizeVectorOp(Tmp2);
Tmp2 = LegalizeOp(Tmp2);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
// FIXME: Returns of gcc generic vectors smaller than a legal type
// should be returned in integer registers!
-
+
// The scalarized value type may not be legal, e.g. it might require
// promotion or expansion. Relegalize the return.
Result = LegalizeOp(Result);
@@ -2520,7 +2520,7 @@
// type should be returned by reference!
SDValue Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
- Result = DAG.getNode(ISD::RET, dl, MVT::Other,
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other,
Tmp1, Lo, Tmp3, Hi,Tmp3);
Result = LegalizeOp(Result);
}
@@ -2561,7 +2561,7 @@
case Promote:
assert(0 && "Can't promote multiple return value yet!");
}
-
+
if (NewValues.size() == Node->getNumOperands())
Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
else
@@ -2599,7 +2599,7 @@
// together.
// We generally can't do this one for long doubles.
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == MVT::f32 &&
+ if (CFP->getValueType(0) == MVT::f32 &&
getTypeAction(MVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
@@ -2636,11 +2636,11 @@
}
}
}
-
+
switch (getTypeAction(ST->getMemoryVT())) {
case Legal: {
Tmp3 = LegalizeOp(ST->getValue());
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
MVT VT = Tmp3.getValueType();
@@ -2663,7 +2663,7 @@
break;
case TargetLowering::Promote:
assert(VT.isVector() && "Unknown legal promote case!");
- Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
+ Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
ST->getSrcValue(), SVOffset, isVolatile,
@@ -2685,7 +2685,7 @@
case Expand: {
unsigned IncrementSize = 0;
SDValue Lo, Hi;
-
+
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
// in the high half of the vector.
@@ -2883,7 +2883,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1);
Tmp1 = Result.getValue(0);
Tmp2 = Result.getValue(1);
-
+
switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
@@ -2895,7 +2895,7 @@
}
break;
case TargetLowering::Expand:
- // Expand to CopyFromReg if the target set
+ // Expand to CopyFromReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
@@ -2918,7 +2918,7 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-
+
switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
@@ -2927,7 +2927,7 @@
if (Tmp1.getNode()) Result = Tmp1;
break;
case TargetLowering::Expand:
- // Expand to CopyToReg if the target set
+ // Expand to CopyToReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
@@ -2982,7 +2982,7 @@
Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
@@ -2993,11 +2993,11 @@
}
case TargetLowering::Expand:
if (Tmp1.getOpcode() == ISD::SETCC) {
- Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
+ Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
Tmp2, Tmp3,
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
} else {
- Result = DAG.getSelectCC(dl, Tmp1,
+ Result = DAG.getSelectCC(dl, Tmp1,
DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE);
}
@@ -3036,10 +3036,10 @@
Tmp3 = LegalizeOp(Node->getOperand(2)); // True
Tmp4 = LegalizeOp(Node->getOperand(3)); // False
SDValue CC = Node->getOperand(4);
-
- LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
+
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
Tmp1, Tmp2, CC, dl);
-
+
// If we didn't get both a LHS and RHS back from LegalizeSetCC,
// the LHS is a legal SETCC itself. In this case, we need to compare
// the result against zero to select between true and false values.
@@ -3065,9 +3065,9 @@
Tmp2 = Node->getOperand(1);
Tmp3 = Node->getOperand(2);
LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
-
- // If we had to Expand the SetCC operands into a SELECT node, then it may
- // not always be possible to return a true LHS & RHS. In this case, just
+
+ // If we had to Expand the SetCC operands into a SELECT node, then it may
+ // not always be possible to return a true LHS & RHS. In this case, just
// return the value we legalized, returned in the LHS
if (Tmp2.getNode() == 0) {
Result = Tmp1;
@@ -3101,7 +3101,7 @@
"Fell off of the edge of the integer world");
assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
"Fell off of the edge of the floating point world");
-
+
// If the target supports SETCC of this type, use it.
if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
break;
@@ -3122,7 +3122,7 @@
// Expand a setcc node into a select_cc of the same condition, lhs, and
// rhs that selects between const 1 (true) and const 0 (false).
MVT VT = Node->getValueType(0);
- Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
+ Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
Tmp3);
break;
@@ -3132,7 +3132,7 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
SDValue CC = Node->getOperand(2);
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
// Everything is legal, see if we should expand this op or something.
@@ -3263,7 +3263,7 @@
// Fall through if the custom lower can't deal with the operation
case TargetLowering::Expand: {
MVT VT = Op.getValueType();
-
+
// See if multiply or divide can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
if (Node->getOpcode() == ISD::MUL) {
@@ -3293,12 +3293,12 @@
}
if (Node->getOpcode() == ISD::MULHS &&
TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
- Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
+ Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
VTs, Tmp1, Tmp2).getNode(),
1);
break;
}
- if (Node->getOpcode() == ISD::MULHU &&
+ if (Node->getOpcode() == ISD::MULHU &&
TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
VTs, Tmp1, Tmp2).getNode(),
@@ -3307,7 +3307,7 @@
}
if (Node->getOpcode() == ISD::SDIV &&
TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
VTs, Tmp1, Tmp2).getNode(),
0);
break;
@@ -3353,7 +3353,7 @@
Result = ExpandLibCall(LC, Node, isSigned, Dummy);
break;
}
-
+
assert(Node->getValueType(0).isVector() &&
"Cannot expand this binary operator!");
// Expand the operation into a bunch of nasty scalar code.
@@ -3381,7 +3381,7 @@
}
}
break;
-
+
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
case ISD::SDIVREM:
@@ -3407,9 +3407,9 @@
Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
break;
}
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "Operation not supported");
case TargetLowering::Custom:
@@ -3436,13 +3436,13 @@
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
- DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
+ DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
break;
}
-
+
// Otherwise, do bitwise ops!
MVT NVT =
Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
@@ -3453,7 +3453,7 @@
}
}
break;
-
+
case ISD::ADDC:
case ISD::SUBC:
Tmp1 = LegalizeOp(Node->getOperand(0));
@@ -3506,7 +3506,7 @@
AddLegalizedOperand(SDValue(Node, 0), Tmp3);
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
return Op.getResNo() ? Tmp4 : Tmp3;
-
+
case ISD::BUILD_PAIR: {
MVT PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
@@ -3554,12 +3554,12 @@
unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
bool isSigned = DivOpc == ISD::SDIV;
MVT VT = Node->getValueType(0);
-
+
// See if remainder can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
if (Node->getOpcode() == ISD::SREM &&
TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
VTs, Tmp1, Tmp2).getNode(), 1);
break;
}
@@ -3644,14 +3644,14 @@
break;
}
}
- // Since VAARG produces two values, make sure to remember that we
+ // Since VAARG produces two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result);
AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.getResNo() ? Tmp1 : Result;
}
-
- case ISD::VACOPY:
+
+ case ISD::VACOPY:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
@@ -3680,7 +3680,7 @@
}
break;
- case ISD::VAEND:
+ case ISD::VAEND:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
@@ -3701,13 +3701,13 @@
break;
}
break;
-
- case ISD::VASTART:
+
+ case ISD::VASTART:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
-
+
switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
@@ -3717,7 +3717,7 @@
break;
}
break;
-
+
case ISD::ROTL:
case ISD::ROTR:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
@@ -3741,7 +3741,7 @@
break;
}
break;
-
+
case ISD::BSWAP:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
@@ -3766,7 +3766,7 @@
break;
}
break;
-
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
@@ -3867,7 +3867,7 @@
}
case ISD::FSQRT:
case ISD::FSIN:
- case ISD::FCOS:
+ case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
@@ -3978,18 +3978,18 @@
int InIx = Node->getOperand(0).getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
+
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the vector input.
- Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
LegalizeOp(Node->getOperand(0)));
break;
} else if (NumElems == 1) {
// Turn this into a bit convert of the scalar input.
- Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
ScalarizeVectorOp(Node->getOperand(0)));
break;
} else {
@@ -4044,7 +4044,7 @@
case Promote:
Result = PromoteOp(Node->getOperand(0));
// For FP, make Op1 a i32
-
+
Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
DTyOp, STyOp, RndOp, SatOp, CvtCode);
break;
@@ -4118,7 +4118,7 @@
break;
case TargetLowering::Promote:
Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
- Node->getOpcode() == ISD::FP_TO_SINT,
+ Node->getOpcode() == ISD::FP_TO_SINT,
dl);
break;
case TargetLowering::Expand:
@@ -4131,12 +4131,12 @@
APInt x = APInt::getSignBit(NVT.getSizeInBits());
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp2 = DAG.getConstantFP(apf, VT);
- Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
+ Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
Node->getOperand(0),
Tmp2, ISD::SETLT);
True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
- DAG.getNode(ISD::FSUB, dl, VT,
+ DAG.getNode(ISD::FSUB, dl, VT,
Node->getOperand(0), Tmp2));
False = DAG.getNode(ISD::XOR, dl, NVT, False,
DAG.getConstant(x, NVT));
@@ -4154,9 +4154,9 @@
// Convert ppcf128 to i32
if (OVT == MVT::ppcf128 && VT == MVT::i32) {
if (Node->getOpcode() == ISD::FP_TO_SINT) {
- Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
Node->getOperand(0), DAG.getValueType(MVT::f64));
- Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
+ Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
DAG.getIntPtrConstant(1));
Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
} else {
@@ -4165,14 +4165,14 @@
Tmp2 = DAG.getConstantFP(apf, OVT);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
Tmp2,
DAG.getNode(ISD::ADD, dl, MVT::i32,
DAG.getNode(ISD::FP_TO_SINT, dl, VT,
DAG.getNode(ISD::FSUB, dl, OVT,
Node->getOperand(0), Tmp2)),
DAG.getConstant(0x80000000, MVT::i32)),
- DAG.getNode(ISD::FP_TO_SINT, dl, VT,
+ DAG.getNode(ISD::FP_TO_SINT, dl, VT,
Node->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
@@ -4315,7 +4315,7 @@
// NOTE: there is a choice here between constantly creating new stack
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
- Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
+ Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
Node->getValueType(0), dl);
} else {
assert(0 && "Unknown op");
@@ -4396,7 +4396,7 @@
SDValue LHS = LegalizeOp(Node->getOperand(0));
SDValue RHS = LegalizeOp(Node->getOperand(1));
- SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
+ SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
LHS, RHS);
MVT OType = Node->getValueType(1);
@@ -4414,8 +4414,8 @@
//
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
- SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
- Node->getOpcode() == ISD::SADDO ?
+ SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
+ Node->getOpcode() == ISD::SADDO ?
ISD::SETEQ : ISD::SETNE);
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
@@ -4426,7 +4426,7 @@
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };
- Result = DAG.getNode(ISD::MERGE_VALUES, dl,
+ Result = DAG.getNode(ISD::MERGE_VALUES, dl,
DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
SDNode *RNode = Result.getNode();
@@ -4456,13 +4456,13 @@
LHS, RHS);
MVT OType = Node->getValueType(1);
SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
- Node->getOpcode () == ISD::UADDO ?
+ Node->getOpcode () == ISD::UADDO ?
ISD::SETULT : ISD::SETUGT);
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };
- Result = DAG.getNode(ISD::MERGE_VALUES, dl,
+ Result = DAG.getNode(ISD::MERGE_VALUES, dl,
DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
SDNode *RNode = Result.getNode();
@@ -4487,17 +4487,17 @@
// FIXME: According to Hacker's Delight, this can be implemented in
// target independent lowering, but it would be inefficient, since it
// requires a division + a branch.
- assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
+ assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
break;
}
break;
}
}
-
+
assert(Result.getValueType() == Op.getValueType() &&
"Bad legalization!");
-
+
// Make sure that the generated code is itself legal.
if (Result != Op)
Result = LegalizeOp(Result);
@@ -4621,7 +4621,7 @@
Node->getValueType(0), dl);
Result = PromoteOp(Result);
break;
-
+
case ISD::FP_EXTEND:
assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
case ISD::FP_ROUND:
@@ -4635,7 +4635,7 @@
DAG.getValueType(VT));
} else {
// Just remove the truncate, it isn't affecting the value.
- Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
Node->getOperand(1));
}
break;
@@ -4674,7 +4674,7 @@
case ISD::SIGN_EXTEND_INREG:
Result = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
Node->getOperand(1));
break;
case ISD::FP_TO_SINT:
@@ -4695,7 +4695,7 @@
// we can use that instead. This allows us to generate better code for
// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
// legal, such as PowerPC.
- if (Node->getOpcode() == ISD::FP_TO_UINT &&
+ if (Node->getOpcode() == ISD::FP_TO_UINT &&
!TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
(TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
@@ -4751,13 +4751,13 @@
DAG.getValueType(VT));
break;
}
-
+
case ISD::ATOMIC_CMP_SWAP: {
AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
Tmp3 = PromoteOp(Node->getOperand(3));
- Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
- AtomNode->getChain(),
+ Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
+ AtomNode->getChain(),
AtomNode->getBasePtr(), Tmp2, Tmp3,
AtomNode->getSrcValue(),
AtomNode->getAlignment());
@@ -4779,7 +4779,7 @@
AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
- AtomNode->getChain(),
+ AtomNode->getChain(),
AtomNode->getBasePtr(), Tmp2,
AtomNode->getSrcValue(),
AtomNode->getAlignment());
@@ -4809,7 +4809,7 @@
Tmp2 = PromoteOp(Node->getOperand(1));
assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
-
+
// Floating point operations will give excess precision that we may not be
// able to tolerate. If we DO allow excess precision, just leave it,
// otherwise excise it.
@@ -4853,7 +4853,7 @@
case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
}
Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
-
+
// Perform FP_ROUND: this is probably overly pessimistic.
if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
@@ -4899,7 +4899,7 @@
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
- Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
+ Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits()/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
@@ -4992,7 +4992,7 @@
// Make sure the result is itself legal.
Result = LegalizeOp(Result);
-
+
// Remember that we promoted this!
AddPromotedOperand(Op, Result);
return Result;
@@ -5009,10 +5009,10 @@
SDValue Vec = Op.getOperand(0);
SDValue Idx = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
-
+
MVT TVT = Vec.getValueType();
unsigned NumElems = TVT.getVectorNumElements();
-
+
switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom: {
@@ -5052,7 +5052,7 @@
Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
Idx.getValueType());
}
-
+
// It's now an extract from the appropriate high or low part. Recurse.
Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
Op = ExpandEXTRACT_VECTOR_ELT(Op);
@@ -5086,9 +5086,9 @@
// is a constant and that the extracted result is a supported hardware type.
SDValue Vec = Op.getOperand(0);
SDValue Idx = LegalizeOp(Op.getOperand(1));
-
+
unsigned NumElems = Vec.getValueType().getVectorNumElements();
-
+
if (NumElems == Op.getValueType().getVectorNumElements()) {
// This must be an access of the desired vector length. Return it.
return Vec;
@@ -5104,7 +5104,7 @@
Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
Idx.getValueType());
}
-
+
// It's now an extract from the appropriate high or low part. Recurse.
Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
return ExpandEXTRACT_SUBVECTOR(Op);
@@ -5120,8 +5120,8 @@
SDValue &RHS,
SDValue &CC,
DebugLoc dl) {
- SDValue Tmp1, Tmp2, Tmp3, Result;
-
+ SDValue Tmp1, Tmp2, Tmp3, Result;
+
switch (getTypeAction(LHS.getValueType())) {
case Legal:
Tmp1 = LegalizeOp(LHS); // LHS
@@ -5300,7 +5300,7 @@
// If this is a comparison of the sign bit, just look at the top part.
// X > -1, x < 0
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
- if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
+ if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
CST->isNullValue()) || // X < 0
(cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
CST->isAllOnesValue())) { // X > -1
@@ -5341,7 +5341,7 @@
Tmp2 = DAG.getNode(ISD::SETCC, dl,
TLI.getSetCCResultType(LHSHi.getValueType()),
LHSHi, RHSHi,CC);
-
+
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
if ((Tmp1C && Tmp1C->isNullValue()) ||
@@ -5432,7 +5432,7 @@
unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
SrcOp.getValueType().getTypeForMVT());
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
-
+
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex();
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
@@ -5442,11 +5442,11 @@
unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
DestVT.getTypeForMVT());
-
+
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
SDValue Store;
-
+
if (SrcSize > SlotSize)
Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
SV, 0, SlotVT, false, SrcAlign);
@@ -5455,11 +5455,11 @@
Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
SV, 0, false, SrcAlign);
}
-
+
// Result is a load from the stack slot.
if (SlotSize == DestSize)
return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
-
+
assert(SlotSize < DestSize && "Unknown extension!");
return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
false, DestAlign);
@@ -5474,7 +5474,7 @@
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
int SPFI = StackPtrFI->getIndex();
- SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
@@ -5485,14 +5485,14 @@
/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
/// support the operation, but do support the resultant vector type.
SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
-
- // If the only non-undef value is the low element, turn this into a
+
+ // If the only non-undef value is the low element, turn this into a
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
unsigned NumElems = Node->getNumOperands();
bool isOnlyLowElement = true;
SDValue SplatValue = Node->getOperand(0);
DebugLoc dl = Node->getDebugLoc();
-
+
// FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
// and use a bitmask instead of a list of elements.
std::map<SDValue, std::vector<unsigned> > Values;
@@ -5501,7 +5501,7 @@
if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
SplatValue.getOpcode() != ISD::UNDEF)
isConstant = false;
-
+
for (unsigned i = 1; i < NumElems; ++i) {
SDValue V = Node->getOperand(i);
Values[V].push_back(i);
@@ -5516,7 +5516,7 @@
V.getOpcode() != ISD::UNDEF)
isConstant = false;
}
-
+
if (isOnlyLowElement) {
// If the low element is an undef too, then this whole things is an undef.
if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
@@ -5525,21 +5525,21 @@
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
Node->getOperand(0));
}
-
+
// If all elements are constants, create a load from the constant pool.
if (isConstant) {
MVT VT = Node->getValueType(0);
std::vector<Constant*> CV;
for (unsigned i = 0, e = NumElems; i != e; ++i) {
- if (ConstantFPSDNode *V =
+ if (ConstantFPSDNode *V =
dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
- } else if (ConstantSDNode *V =
+ } else if (ConstantSDNode *V =
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
- const Type *OpNTy =
+ const Type *OpNTy =
Node->getOperand(0).getValueType().getTypeForMVT();
CV.push_back(UndefValue::get(OpNTy));
}
@@ -5551,7 +5551,7 @@
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
}
-
+
if (SplatValue.getNode()) { // Splat of one value?
// Build the shuffle constant vector: <0, 0, 0, 0>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
@@ -5563,18 +5563,18 @@
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
// Get the splatted value into the low element of a vector register.
- SDValue LowValVec =
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
+ SDValue LowValVec =
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Node->getValueType(0), SplatValue);
-
+
// Return shuffle(LowValVec, undef, <0,0,0,0>)
- return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
Node->getValueType(0), LowValVec,
DAG.getUNDEF(Node->getValueType(0)),
SplatMask);
}
}
-
+
// If there are only two unique elements, we may be able to turn this into a
// vector shuffle.
if (Values.size() == 2) {
@@ -5586,12 +5586,12 @@
Val2 = MI->first;
else
Val2 = (++MI)->first;
-
- // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
+
+ // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
// vector shuffle has the undef vector on the RHS.
if (Val1.getOpcode() == ISD::UNDEF)
std::swap(Val1, Val2);
-
+
// Build the shuffle constant vector: e.g. <0, 4, 0, 4>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT MaskEltVT = MaskVT.getVectorElementType();
@@ -5609,7 +5609,7 @@
MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
else
MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
-
+
SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
@@ -5625,7 +5625,7 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
}
}
-
+
// Otherwise, we can't handle this case efficiently. Allocate a sufficiently
// aligned object on the stack, store each element into it, then load
// the result as a vector.
@@ -5642,23 +5642,23 @@
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
// Ignore undef elements.
if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-
+
unsigned Offset = TypeByteSize*i;
-
+
SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
-
+
Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
Idx, SV, Offset));
}
-
+
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
-
+
// Result is a load from the stack slot.
return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
}
@@ -5717,7 +5717,7 @@
Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
Hi = DAG.getNode(ISD::OR, dl, NVT,
DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SRL, dl, NVT, InL,
+ DAG.getNode(ISD::SRL, dl, NVT, InL,
DAG.getConstant(NVTBits-Cst, ShTy)));
}
return true;
@@ -5726,7 +5726,7 @@
Lo = DAG.getConstant(0, NVT);
Hi = DAG.getConstant(0, NVT);
} else if (Cst > NVTBits) {
- Lo = DAG.getNode(ISD::SRL, dl, NVT,
+ Lo = DAG.getNode(ISD::SRL, dl, NVT,
InH, DAG.getConstant(Cst-NVTBits,ShTy));
Hi = DAG.getConstant(0, NVT);
} else if (Cst == NVTBits) {
@@ -5735,7 +5735,7 @@
} else {
Lo = DAG.getNode(ISD::OR, dl, NVT,
DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SHL, dl, NVT, InH,
+ DAG.getNode(ISD::SHL, dl, NVT, InH,
DAG.getConstant(NVTBits-Cst, ShTy)));
Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
}
@@ -5756,27 +5756,27 @@
} else {
Lo = DAG.getNode(ISD::OR, dl, NVT,
DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SHL, dl,
+ DAG.getNode(ISD::SHL, dl,
NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
}
return true;
}
}
-
+
// Okay, the shift amount isn't constant. However, if we can tell that it is
// >= 32 or < 32, we can still simplify it, without knowing the actual value.
APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
-
+
// If we know that if any of the high bits of the shift amount are one, then
// we can do this as a couple of simple shifts.
if (KnownOne.intersects(Mask)) {
// Mask out the high bit, which we know is set.
Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
DAG.getConstant(~Mask, Amt.getValueType()));
-
+
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
ExpandOp(Op, InL, InH);
@@ -5796,7 +5796,7 @@
return true;
}
}
-
+
// If we know that the high bits of the shift amount are all zero, then we can
// do this as a couple of simple shifts.
if ((KnownZero & Mask) == Mask) {
@@ -5804,7 +5804,7 @@
SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
DAG.getConstant(NVTBits, Amt.getValueType()),
Amt);
-
+
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
ExpandOp(Op, InL, InH);
@@ -5829,7 +5829,7 @@
return true;
}
}
-
+
return false;
}
@@ -5841,17 +5841,17 @@
SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
bool isSigned, SDValue &Hi) {
assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
- // The input chain to this libcall is the entry node of the function.
+ // The input chain to this libcall is the entry node of the function.
// Legalizing the call will automatically add the previous call to the
// dependence.
SDValue InChain = DAG.getEntryNode();
-
+
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
MVT ArgVT = Node->getOperand(i).getValueType();
const Type *ArgTy = ArgVT.getTypeForMVT();
- Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
+ Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@@ -5927,7 +5927,7 @@
Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
Tmp1, DAG.getValueType(Op.getValueType()));
} else {
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
Op.getValueType());
}
if (Result.getNode())
@@ -5963,9 +5963,9 @@
SplitVectorOp(Source, Lo, Hi);
MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
DestTy.getVectorNumElements() / 2);
- SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
+ SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
Lo, dl);
- SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
+ SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
Hi, dl);
return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
HiResult));
@@ -6006,7 +6006,7 @@
// signed, then adjust the result if the sign bit is set.
SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
- SDValue SignSet = DAG.getSetCC(dl,
+ SDValue SignSet = DAG.getSetCC(dl,
TLI.getSetCCResultType(Hi.getValueType()),
Hi, DAG.getConstant(0, Hi.getValueType()),
ISD::SETLT);
@@ -6032,7 +6032,7 @@
CPIdx,
PseudoSourceValue::getConstantPool(), 0,
MVT::f32, false, Alignment);
- else
+ else
assert(0 && "Unexpected conversion");
MVT SCVT = SignedConv.getValueType();
@@ -6095,19 +6095,19 @@
DebugLoc dl) {
if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
-
+
// Get the stack frame index of a 8 byte buffer.
SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
-
+
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
// set up Hi and Lo (into buffer) address based on endian
SDValue Hi = StackSlot;
- SDValue Lo = DAG.getNode(ISD::ADD, dl,
+ SDValue Lo = DAG.getNode(ISD::ADD, dl,
TLI.getPointerTy(), StackSlot,WordOff);
if (TLI.isLittleEndian())
std::swap(Hi, Lo);
-
+
// if signed map to unsigned space
SDValue Op0Mapped;
if (isSigned) {
@@ -6295,7 +6295,7 @@
// Otherwise, try a larger type.
}
-
+
// Okay, we found the operation and type to use.
SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
@@ -6363,7 +6363,7 @@
/// ExpandBitCount - Expand the specified bitcount instruction into operations.
///
-SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
+SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
DebugLoc dl) {
switch (Opc) {
default: assert(0 && "Cannot expand this yet!");
@@ -6382,7 +6382,7 @@
VT.getVectorElementType().getSizeInBits() : len;
SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
- Op = DAG.getNode(ISD::ADD, dl, VT,
+ Op = DAG.getNode(ISD::ADD, dl, VT,
DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
@@ -6405,7 +6405,7 @@
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
- Op = DAG.getNode(ISD::OR, dl, VT, Op,
+ Op = DAG.getNode(ISD::OR, dl, VT, Op,
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
}
Op = DAG.getNOT(dl, Op, VT);
@@ -6459,8 +6459,8 @@
case ISD::CopyFromReg:
assert(0 && "CopyFromReg must be legal!");
case ISD::FP_ROUND_INREG:
- if (VT == MVT::ppcf128 &&
- TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
+ if (VT == MVT::ppcf128 &&
+ TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
TargetLowering::Custom) {
SDValue SrcLo, SrcHi, Src;
ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
@@ -6505,7 +6505,7 @@
APInt api = CFP->getValueAPF().bitcastToAPInt();
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
MVT::f64);
- Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
+ Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
MVT::f64);
break;
}
@@ -6519,7 +6519,7 @@
Lo = Node->getOperand(0);
Hi = Node->getOperand(1);
break;
-
+
case ISD::MERGE_VALUES:
if (Node->getNumValues() == 1) {
ExpandOp(Op.getOperand(0), Lo, Hi);
@@ -6533,12 +6533,12 @@
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
break;
-
+
case ISD::SIGN_EXTEND_INREG:
ExpandOp(Node->getOperand(0), Lo, Hi);
// sext_inreg the low part if needed.
Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
-
+
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
@@ -6553,7 +6553,7 @@
Lo = TempLo;
break;
}
-
+
case ISD::CTPOP:
ExpandOp(Node->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
@@ -6605,7 +6605,7 @@
std::swap(Lo, Hi);
break;
}
-
+
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Node);
SDValue Ch = LD->getChain(); // Legalize the chain.
@@ -6660,7 +6660,7 @@
ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
break;
}
-
+
if (EVT == NVT)
Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
SVOffset, isVolatile, Alignment);
@@ -6668,7 +6668,7 @@
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
SVOffset, EVT, isVolatile,
Alignment);
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
@@ -6748,12 +6748,12 @@
// The high part is just a zero.
Hi = DAG.getConstant(0, NVT);
break;
-
+
case ISD::TRUNCATE: {
// The input value must be larger than this value. Expand *it*.
SDValue NewLo;
ExpandOp(Node->getOperand(0), NewLo, Hi);
-
+
// The low part is now either the right size, or it is closer. If not the
// right size, make an illegal truncate so we recursively expand it.
if (NewLo.getValueType() != Node->getValueType(0))
@@ -6761,7 +6761,7 @@
ExpandOp(NewLo, Lo, Hi);
break;
}
-
+
case ISD::BIT_CONVERT: {
SDValue Tmp;
if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
@@ -6793,13 +6793,13 @@
// Turn this into a load/store pair by default.
if (Tmp.getNode() == 0)
Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
-
+
ExpandOp(Tmp, Lo, Hi);
break;
}
case ISD::READCYCLECOUNTER: {
- assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
+ assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
TargetLowering::Custom &&
"Must custom expand ReadCycleCounter");
SDValue Tmp = TLI.LowerOperation(Op, DAG);
@@ -6833,7 +6833,7 @@
ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
- SDValue Replace =
+ SDValue Replace =
DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
Op.getOperand(0), Op.getOperand(1), In2,
Anode->getSrcValue(), Anode->getAlignment());
@@ -6880,7 +6880,7 @@
case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
case Promote: Op = PromoteOp (Node->getOperand(0)); break;
}
-
+
Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
// Now that the custom expander is done, expand the result.
@@ -6910,12 +6910,12 @@
break;
}
}
-
- // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
+
+ // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
// this X << 1 as X+X.
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
if (ShAmt->getAPIntValue() == 1 &&
- TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
+ TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
SDValue LoOps[2], HiOps[3];
ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
@@ -6929,7 +6929,7 @@
break;
}
}
-
+
// If we can emit an efficient shift operation, do so now.
if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
break;
@@ -6939,7 +6939,7 @@
TLI.getOperationAction(ISD::SHL_PARTS, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
- ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
+ ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
ShiftAmt, Lo, Hi, dl);
break;
}
@@ -6962,7 +6962,7 @@
break;
}
}
-
+
// If we can emit an efficient shift operation, do so now.
if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
break;
@@ -6972,7 +6972,7 @@
TLI.getOperationAction(ISD::SRA_PARTS, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
- ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
+ ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
ShiftAmt, Lo, Hi, dl);
break;
}
@@ -7066,12 +7066,12 @@
SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
Lo, LoOps[0], ISD::SETULT);
SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
- DAG.getConstant(1, NVT),
+ DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
Lo, LoOps[1], ISD::SETULT);
SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
- DAG.getConstant(1, NVT),
+ DAG.getConstant(1, NVT),
Carry1);
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
} else {
@@ -7079,14 +7079,14 @@
Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
- DAG.getConstant(1, NVT),
+ DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
}
break;
}
}
-
+
case ISD::ADDC:
case ISD::SUBC: {
// Expand the subcomponents.
@@ -7096,7 +7096,7 @@
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
-
+
if (Node->getOpcode() == ISD::ADDC) {
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
@@ -7119,11 +7119,11 @@
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
-
+
Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
HiOps[2] = Lo.getValue(1);
Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
-
+
// Remember that we legalized the flag.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
break;
@@ -7137,7 +7137,7 @@
break;
}
}
-
+
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
@@ -7276,7 +7276,7 @@
}
case ISD::FSQRT:
case ISD::FSIN:
- case ISD::FCOS:
+ case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
@@ -7420,19 +7420,19 @@
if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
static const uint64_t zero = 0;
if (isSigned) {
- Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
+ Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
Node->getOperand(0)));
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
} else {
static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
- Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
+ Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
Node->getOperand(0)));
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
// X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
MVT::ppcf128, Node->getOperand(0),
- DAG.getConstant(0, MVT::i32),
+ DAG.getConstant(0, MVT::i32),
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP(
APFloat(APInt(128, 2, TwoE32)),
@@ -7452,7 +7452,7 @@
// x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
Node->getOperand(0),
- DAG.getConstant(0, MVT::i64),
+ DAG.getConstant(0, MVT::i64),
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP(
APFloat(APInt(128, 2, TwoE64)),
@@ -7514,9 +7514,9 @@
Hi = I->second.second;
return;
}
-
+
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG);
#endif
@@ -7553,8 +7553,8 @@
SDValue Mask = Node->getOperand(2);
SmallVector<SDValue, 8> Ops;
MVT PtrVT = TLI.getPointerTy();
-
- // Insert all of the elements from the input that are needed. We use
+
+ // Insert all of the elements from the input that are needed. We use
// buildvector of extractelement here because the input vectors will have
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
@@ -7574,7 +7574,7 @@
}
Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
Ops.clear();
-
+
for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
@@ -7594,11 +7594,11 @@
break;
}
case ISD::BUILD_VECTOR: {
- SmallVector<SDValue, 8> LoOps(Node->op_begin(),
+ SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumElts_Lo);
Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
- SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
+ SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
Node->op_end());
Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
break;
@@ -7612,12 +7612,12 @@
} else {
SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumSubvectors);
- Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
+ Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
&LoOps[0], LoOps.size());
SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
Node->op_end());
- Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
+ Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
&HiOps[0], HiOps.size());
}
break;
@@ -7630,7 +7630,7 @@
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
- Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
+ Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
IdxVT));
} else {
@@ -7664,15 +7664,15 @@
SDValue CondLHS = Node->getOperand(0);
SDValue CondRHS = Node->getOperand(1);
SDValue CondCode = Node->getOperand(4);
-
+
SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(2), LL, LH);
SplitVectorOp(Node->getOperand(3), RL, RH);
-
+
// Handle a simple select with vector operands.
Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
LL, RL, CondCode);
- Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
+ Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
LH, RH, CondCode);
break;
}
@@ -7706,7 +7706,7 @@
SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
-
+
Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
break;
@@ -7796,12 +7796,12 @@
Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT_Hi, Ch, Ptr, Offset,
SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
-
+
// Build a factor node to remember that this load is independent of the
// other one.
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
break;
@@ -7833,9 +7833,9 @@
break;
}
}
-
+
// Remember in a map if the values will be reused later.
- bool isNew =
+ bool isNew =
SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
assert(isNew && "Value already split?!?");
isNew = isNew;
@@ -7851,14 +7851,14 @@
DebugLoc dl = Node->getDebugLoc();
MVT NewVT = Op.getValueType().getVectorElementType();
assert(Op.getValueType().getVectorNumElements() == 1);
-
+
// See if we already scalarized it.
std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
if (I != ScalarizedNodes.end()) return I->second;
-
+
SDValue Result;
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG); cerr << "\n";
#endif
@@ -7880,7 +7880,7 @@
case ISD::OR:
case ISD::XOR:
Result = DAG.getNode(Node->getOpcode(), dl,
- NewVT,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)),
ScalarizeVectorOp(Node->getOperand(1)));
break;
@@ -7904,7 +7904,7 @@
case ISD::TRUNCATE:
case ISD::FP_EXTEND:
Result = DAG.getNode(Node->getOpcode(), dl,
- NewVT,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)));
break;
case ISD::CONVERT_RNDSAT: {
@@ -7920,7 +7920,7 @@
case ISD::FPOWI:
case ISD::FP_ROUND:
Result = DAG.getNode(Node->getOpcode(), dl,
- NewVT,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)),
Node->getOperand(1));
break;
@@ -7937,7 +7937,7 @@
assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
-
+
Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT, Ch, Ptr, Offset, SV, SVOffset,
MemoryVT.getVectorElementType(),
@@ -7969,7 +7969,7 @@
break;
}
case ISD::EXTRACT_SUBVECTOR:
- Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
+ Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
Node->getOperand(0), Node->getOperand(1));
break;
case ISD::BIT_CONVERT: {
@@ -7985,7 +7985,7 @@
ScalarizeVectorOp(Op.getOperand(2)));
break;
case ISD::SELECT_CC:
- Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
Node->getOperand(1),
ScalarizeVectorOp(Op.getOperand(2)),
ScalarizeVectorOp(Op.getOperand(3)),
@@ -8016,7 +8016,7 @@
SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
if (I != WidenNodes.end()) return I->second;
-
+
MVT VT = Op.getValueType();
assert(VT.isVector() && "Cannot widen non-vector type!");
@@ -8040,7 +8040,7 @@
// code to pack/unpack the results. It is the function that calls widen
// that is responsible for seeing this doesn't happen.
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG);
#endif
@@ -8066,8 +8066,8 @@
for (unsigned i = NumElts; i < NewNumElts; ++i) {
NewOps.push_back(DAG.getUNDEF(EVT));
}
- Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
- &NewOps[0], NewOps.size());
+ Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
+ &NewOps[0], NewOps.size());
break;
}
case ISD::INSERT_VECTOR_ELT: {
@@ -8097,17 +8097,17 @@
else {
NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
PermOp.getOperand(i).getValueType()));
- }
+ }
}
}
for (unsigned i = NumElts; i < NewNumElts; ++i) {
NewOps.push_back(DAG.getUNDEF(PVT));
}
-
- SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
+
+ SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
MVT::getVectorVT(PVT, NewOps.size()),
- &NewOps[0], NewOps.size());
-
+ &NewOps[0], NewOps.size());
+
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
break;
}
@@ -8128,7 +8128,7 @@
// Converts between two different types so we need to determine
// the correct widen type for the input operand.
MVT InVT = Tmp1.getValueType();
- unsigned WidenSize = WidenVT.getSizeInBits();
+ unsigned WidenSize = WidenVT.getSizeInBits();
if (InVT.isVector()) {
MVT InEltVT = InVT.getVectorElementType();
unsigned InEltSize = InEltVT.getSizeInBits();
@@ -8221,7 +8221,7 @@
break;
}
case ISD::FPOW:
- case ISD::FPOWI:
+ case ISD::FPOWI:
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
@@ -8337,7 +8337,7 @@
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
break;
}
-
+
case ISD::SELECT_CC: {
// Determine new condition widen type and widen
SDValue Cond1 = Node->getOperand(0);
@@ -8395,7 +8395,7 @@
} // end switch (Node->getOpcode())
- assert(Result.getNode() && "Didn't set a result!");
+ assert(Result.getNode() && "Didn't set a result!");
if (Result != Op)
Result = LegalizeOp(Result);
@@ -8455,7 +8455,7 @@
isVolatile, Alignment);
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
LdChain.push_back(LdOp.getValue(1));
-
+
// Check if we can load the element with one instruction
if (LdWidth == EVTWidth) {
return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
@@ -8465,7 +8465,7 @@
unsigned Idx = 1;
LdWidth -= EVTWidth;
unsigned Offset = 0;
-
+
while (LdWidth > 0) {
unsigned Increment = EVTWidth / 8;
Offset += Increment;
@@ -8482,14 +8482,14 @@
Idx = Idx * (oEVTWidth/EVTWidth);
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
}
-
+
SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
SVOffset+Offset, isVolatile,
MinAlign(Alignment, Offset));
LdChain.push_back(LdOp.getValue(1));
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
DAG.getIntPtrConstant(Idx++));
-
+
LdWidth -= EVTWidth;
}
@@ -8505,14 +8505,14 @@
// to memory mapping is strange (e.g., vector elements are not
// stored in some sequential order).
- // It must be true that the widen vector type is bigger than where
+ // It must be true that the widen vector type is bigger than where
// we need to load from.
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
MVT LdVT = LD->getMemoryVT();
DebugLoc dl = LD->getDebugLoc();
assert(LdVT.isVector() && NVT.isVector());
assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
-
+
// Load information
SDValue Chain = LD->getChain();
SDValue BasePtr = LD->getBasePtr();
@@ -8521,7 +8521,7 @@
bool isVolatile = LD->isVolatile();
const Value *SV = LD->getSrcValue();
unsigned int LdWidth = LdVT.getSizeInBits();
-
+
// Load value as a large register
SDValueVector LdChain;
Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
@@ -8532,7 +8532,7 @@
return true;
}
else {
- TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&LdChain[0], LdChain.size());
return false;
}
@@ -8552,7 +8552,7 @@
// Breaks the stores into a series of power of 2 width stores. For any
// width, we convert the vector to the vector of element size that we
// want to store. This avoids requiring a stack convert.
-
+
// Find a width of the element type we can store with
MVT VVT = ValOp.getValueType();
MVT EVT, VecEVT;
@@ -8571,17 +8571,17 @@
if (StWidth == EVTWidth) {
return;
}
-
+
unsigned Idx = 1;
StWidth -= EVTWidth;
unsigned Offset = 0;
-
+
while (StWidth > 0) {
unsigned Increment = EVTWidth / 8;
Offset += Increment;
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getIntPtrConstant(Increment));
-
+
if (StWidth < EVTWidth) {
// Our current type we are using is too large, use a smaller size by
// using a smaller power of 2
@@ -8592,7 +8592,7 @@
Idx = Idx * (oEVTWidth/EVTWidth);
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
}
-
+
EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
DAG.getIntPtrConstant(Idx++));
StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
@@ -8611,7 +8611,7 @@
// be stored as a word). This will not work when a vector register
// to memory mapping is strange (e.g., vector elements are not
// stored in some sequential order).
-
+
MVT StVT = ST->getMemoryVT();
SDValue ValOp = ST->getValue();
DebugLoc dl = ST->getDebugLoc();
@@ -8620,7 +8620,7 @@
std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
if (I != WidenNodes.end())
ValOp = I->second;
-
+
MVT VVT = ValOp.getValueType();
// It must be true that we the widen vector type is bigger than where
@@ -8636,7 +8636,7 @@
ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
if (StChain.size() == 1)
return StChain[0];
- else
+ else
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&StChain[0], StChain.size());
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Feb 17 16:15:04 2009
@@ -150,7 +150,7 @@
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
SDValue Op3 = GetPromotedInteger(N->getOperand(3));
- SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
+ SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
N->getMemoryVT(), N->getChain(), N->getBasePtr(),
Op2, Op3, N->getSrcValue(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
@@ -2067,7 +2067,7 @@
}
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
- LHSHi, RHSHi, ISD::SETEQ, false,
+ LHSHi, RHSHi, ISD::SETEQ, false,
DagCombineInfo, dl);
if (!NewLHS.getNode())
NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Feb 17 16:15:04 2009
@@ -126,7 +126,7 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
- return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
+ return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
Op0, DAG.getValueType(NewVT),
DAG.getValueType(Op0.getValueType()),
N->getOperand(3),
@@ -544,7 +544,7 @@
SDValue SatOp = N->getOperand(4);
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
- Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
+ Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
CvtCode);
Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
CvtCode);
@@ -1227,7 +1227,7 @@
if (InVTNumElts % WidenNumElts == 0) {
// Extract the input and convert the shorten input vector.
return DAG.getNode(Opcode, dl, WidenVT,
- DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
+ DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
InOp, DAG.getIntPtrConstant(0)));
}
}
@@ -1953,7 +1953,7 @@
if (StChain.size() == 1)
return StChain[0];
else
- return DAG.getNode(ISD::TokenFactor, dl,
+ return DAG.getNode(ISD::TokenFactor, dl,
MVT::Other,&StChain[0],StChain.size());
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 17 16:15:04 2009
@@ -77,12 +77,12 @@
bool ConstantFPSDNode::isValueValidForType(MVT VT,
const APFloat& Val) {
assert(VT.isFloatingPoint() && "Can only convert between FP types");
-
+
// PPC long double cannot be converted to any other type.
if (VT == MVT::ppcf128 ||
&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
-
+
// convert modifies in place, so make a copy.
APFloat Val2 = APFloat(Val);
bool losesInfo;
@@ -101,18 +101,18 @@
// Look through a bit convert.
if (N->getOpcode() == ISD::BIT_CONVERT)
N = N->getOperand(0).getNode();
-
+
if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
-
+
unsigned i = 0, e = N->getNumOperands();
-
+
// Skip over all of the undef values.
while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
++i;
-
+
// Do not accept an all-undef vector.
if (i == e) return false;
-
+
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements.
SDValue NotZero = N->getOperand(i);
@@ -125,7 +125,7 @@
return false;
} else
return false;
-
+
// Okay, we have at least one ~0 value, check to see if the rest match or are
// undefs.
for (++i; i != e; ++i)
@@ -142,18 +142,18 @@
// Look through a bit convert.
if (N->getOpcode() == ISD::BIT_CONVERT)
N = N->getOperand(0).getNode();
-
+
if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
-
+
unsigned i = 0, e = N->getNumOperands();
-
+
// Skip over all of the undef values.
while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
++i;
-
+
// Do not accept an all-undef vector.
if (i == e) return false;
-
+
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements.
SDValue Zero = N->getOperand(i);
@@ -165,7 +165,7 @@
return false;
} else
return false;
-
+
// Okay, we have at least one ~0 value, check to see if the rest match or are
// undefs.
for (++i; i != e; ++i)
@@ -271,11 +271,11 @@
// care about orderedness, and is true when ordered.
if (Op > ISD::SETTRUE2)
Op &= ~16; // Clear the U bit if the N bit is set.
-
+
// Canonicalize illegal integer setcc's.
if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
Op = ISD::SETNE;
-
+
return ISD::CondCode(Op);
}
@@ -291,7 +291,7 @@
// Combine all of the condition bits.
ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
-
+
// Canonicalize illegal integer setcc's.
if (isInteger) {
switch (Result) {
@@ -303,7 +303,7 @@
case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
}
}
-
+
return Result;
}
@@ -324,7 +324,7 @@
/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
/// solely with their pointer.
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
- ID.AddPointer(VTList.VTs);
+ ID.AddPointer(VTList.VTs);
}
/// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
@@ -348,7 +348,7 @@
}
static void AddNodeIDNode(FoldingSetNodeID &ID,
- unsigned short OpC, SDVTList VTList,
+ unsigned short OpC, SDVTList VTList,
const SDValue *OpList, unsigned N) {
AddNodeIDOpcode(ID, OpC);
AddNodeIDValueTypes(ID, VTList);
@@ -524,14 +524,14 @@
HandleSDNode Dummy(getRoot());
SmallVector<SDNode*, 128> DeadNodes;
-
+
// Add all obviously-dead nodes to the DeadNodes worklist.
for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I)
if (I->use_empty())
DeadNodes.push_back(I);
RemoveDeadNodes(DeadNodes);
-
+
// If the root changed (e.g. it was a dead load, update the root).
setRoot(Dummy.getValue());
}
@@ -545,10 +545,10 @@
// worklist.
while (!DeadNodes.empty()) {
SDNode *N = DeadNodes.pop_back_val();
-
+
if (UpdateListener)
UpdateListener->NodeDeleted(N, 0);
-
+
// Take the node out of the appropriate CSE map.
RemoveNodeFromCSEMaps(N);
@@ -577,7 +577,7 @@
// First take this out of the appropriate CSE map.
RemoveNodeFromCSEMaps(N);
- // Finally, remove uses due to operands of this node, remove from the
+ // Finally, remove uses due to operands of this node, remove from the
// AllNodes list, and delete the node.
DeleteNodeNotInCSEMaps(N);
}
@@ -595,7 +595,7 @@
void SelectionDAG::DeallocateNode(SDNode *N) {
if (N->OperandsNeedDelete)
delete[] N->OperandList;
-
+
// Set the opcode to DELETED_NODE to help catch bugs when node
// memory is reallocated.
N->NodeType = ISD::DELETED_NODE;
@@ -643,7 +643,7 @@
break;
}
#ifndef NDEBUG
- // Verify that the node was actually in one of the CSE maps, unless it has a
+ // Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
@@ -675,7 +675,7 @@
ReplaceAllUsesWith(N, Existing, UpdateListener);
// N is now dead. Inform the listener if it exists and delete it.
- if (UpdateListener)
+ if (UpdateListener)
UpdateListener->NodeDeleted(N, Existing);
DeleteNodeNotInCSEMaps(N);
return;
@@ -684,12 +684,12 @@
// If the node doesn't already exist, we updated it. Inform a listener if
// it exists.
- if (UpdateListener)
+ if (UpdateListener)
UpdateListener->NodeUpdated(N);
}
/// FindModifiedNodeSlot - Find a slot for the specified node if its operands
-/// were replaced with those specified. If this node is never memoized,
+/// were replaced with those specified. If this node is never memoized,
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
@@ -705,10 +705,10 @@
}
/// FindModifiedNodeSlot - Find a slot for the specified node if its operands
-/// were replaced with those specified. If this node is never memoized,
+/// were replaced with those specified. If this node is never memoized,
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
-SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
+SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
SDValue Op1, SDValue Op2,
void *&InsertPos) {
if (doNotCSE(N))
@@ -723,10 +723,10 @@
/// FindModifiedNodeSlot - Find a slot for the specified node if its operands
-/// were replaced with those specified. If this node is never memoized,
+/// were replaced with those specified. If this node is never memoized,
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
-SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
+SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
const SDValue *Ops,unsigned NumOps,
void *&InsertPos) {
if (doNotCSE(N))
@@ -910,7 +910,7 @@
SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
-
+
MVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
@@ -1259,7 +1259,7 @@
const Type *Ty = VT.getTypeForMVT();
unsigned StackAlign =
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
-
+
int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
return getFrameIndex(FrameIdx, TLI.getPointerTy());
}
@@ -1289,7 +1289,7 @@
case ISD::SETFALSE2: return getConstant(0, VT);
case ISD::SETTRUE:
case ISD::SETTRUE2: return getConstant(1, VT);
-
+
case ISD::SETOEQ:
case ISD::SETOGT:
case ISD::SETOGE:
@@ -1303,12 +1303,12 @@
assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!");
break;
}
-
+
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) {
const APInt &C2 = N2C->getAPIntValue();
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
const APInt &C1 = N1C->getAPIntValue();
-
+
switch (Cond) {
default: assert(0 && "Unknown integer setcc!");
case ISD::SETEQ: return getConstant(C1 == C2, VT);
@@ -1333,29 +1333,29 @@
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
switch (Cond) {
default: break;
- case ISD::SETEQ: if (R==APFloat::cmpUnordered)
+ case ISD::SETEQ: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
- case ISD::SETNE: if (R==APFloat::cmpUnordered)
+ case ISD::SETNE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpLessThan, VT);
- case ISD::SETLT: if (R==APFloat::cmpUnordered)
+ case ISD::SETLT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
- case ISD::SETGT: if (R==APFloat::cmpUnordered)
+ case ISD::SETGT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
- case ISD::SETLE: if (R==APFloat::cmpUnordered)
+ case ISD::SETLE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
R==APFloat::cmpEqual, VT);
- case ISD::SETGE: if (R==APFloat::cmpUnordered)
+ case ISD::SETGE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
@@ -1392,11 +1392,11 @@
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
/// this predicate to simplify operations downstream. Mask is known to be zero
/// for bits that V cannot have.
-bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
+bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
unsigned Depth) const {
APInt KnownZero, KnownOne;
ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
return (KnownZero & Mask) == Mask;
}
@@ -1404,7 +1404,7 @@
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
/// processing.
-void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
+void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
APInt &KnownZero, APInt &KnownOne,
unsigned Depth) const {
unsigned BitWidth = Mask.getBitWidth();
@@ -1414,7 +1414,7 @@
KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
if (Depth == 6 || Mask == 0)
return; // Limit search depth.
-
+
APInt KnownZero2, KnownOne2;
switch (Op.getOpcode()) {
@@ -1428,8 +1428,8 @@
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero,
KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
// Output known-1 bits are only known if set in both the LHS & RHS.
KnownOne &= KnownOne2;
@@ -1440,9 +1440,9 @@
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne,
KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
-
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
// Output known-0 bits are only known if clear in both the LHS & RHS.
KnownZero &= KnownZero2;
// Output known-1 are known to be set if set in either the LHS | RHS.
@@ -1451,9 +1451,9 @@
case ISD::XOR: {
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
-
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
// Output known-0 bits are known if clear or set in both the LHS & RHS.
APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
// Output known-1 are known to be set if set in only one of the LHS, RHS.
@@ -1510,9 +1510,9 @@
case ISD::SELECT:
ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
-
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
// Only known if known in both the LHS and RHS.
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
@@ -1520,9 +1520,9 @@
case ISD::SELECT_CC:
ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
-
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
// Only known if known in both the LHS and RHS.
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
@@ -1553,7 +1553,7 @@
ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt),
KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero <<= ShAmt;
KnownOne <<= ShAmt;
// low bits known zero.
@@ -1571,7 +1571,7 @@
ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt),
KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt);
@@ -1593,17 +1593,17 @@
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
if (HighBits.getBoolValue())
InDemandedMask |= APInt::getSignBit(BitWidth);
-
+
ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt);
-
+
// Handle the sign bits.
APInt SignBit = APInt::getSignBit(BitWidth);
SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask.
-
+
if (KnownZero.intersects(SignBit)) {
KnownZero |= HighBits; // New bits are known zero.
} else if (KnownOne.intersects(SignBit)) {
@@ -1614,24 +1614,24 @@
case ISD::SIGN_EXTEND_INREG: {
MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
unsigned EBits = EVT.getSizeInBits();
-
- // Sign extension. Compute the demanded bits in the result that are not
+
+ // Sign extension. Compute the demanded bits in the result that are not
// present in the input.
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask;
APInt InSignBit = APInt::getSignBit(EBits);
APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits);
-
+
// If the sign extended bits are demanded, we know that the sign
// bit is demanded.
InSignBit.zext(BitWidth);
if (NewBits.getBoolValue())
InputDemandedBits |= InSignBit;
-
+
ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
-
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+
// If the sign bit of the input is known set or clear, then we know the
// top bits of the result.
if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear
@@ -1738,7 +1738,7 @@
KnownZero.zext(InBits);
KnownOne.zext(InBits);
ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero.trunc(BitWidth);
KnownOne.trunc(BitWidth);
break;
@@ -1746,7 +1746,7 @@
case ISD::AssertZext: {
MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
- ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
+ ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
KnownOne, Depth+1);
KnownZero |= (~InMask) & Mask;
return;
@@ -1755,7 +1755,7 @@
// All bits are zero except the low bit.
KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
return;
-
+
case ISD::SUB: {
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
// We know that the top bits of C-X are clear if X contains less bits
@@ -1786,11 +1786,11 @@
// low 3 bits clear.
APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes());
ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1);
- assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
KnownZeroOut = std::min(KnownZeroOut,
KnownZero2.countTrailingOnes());
@@ -1867,7 +1867,7 @@
unsigned VTBits = VT.getSizeInBits();
unsigned Tmp, Tmp2;
unsigned FirstAnswer = 1;
-
+
if (Depth == 6)
return 1; // Limit search depth.
@@ -1879,26 +1879,26 @@
case ISD::AssertZext:
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
return VTBits-Tmp;
-
+
case ISD::Constant: {
const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
// If negative, return # leading ones.
if (Val.isNegative())
return Val.countLeadingOnes();
-
+
// Return # leading zeros.
return Val.countLeadingZeros();
}
-
+
case ISD::SIGN_EXTEND:
Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
-
+
case ISD::SIGN_EXTEND_INREG:
// Max of the input and what this extends.
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
Tmp = VTBits-Tmp+1;
-
+
Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
return std::max(Tmp, Tmp2);
@@ -1958,7 +1958,7 @@
case ISD::ROTR:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned RotAmt = C->getZExtValue() & (VTBits-1);
-
+
// Handle rotate right by N like a rotate left by 32-N.
if (Op.getOpcode() == ISD::ROTR)
RotAmt = (VTBits-RotAmt) & (VTBits-1);
@@ -1974,34 +1974,34 @@
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
if (Tmp == 1) return 1; // Early out.
-
+
// Special case decrementing a value (ADD X, -1):
if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (CRHS->isAllOnesValue()) {
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VTBits);
ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
-
+
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
if ((KnownZero | APInt(VTBits, 1)) == Mask)
return VTBits;
-
+
// If we are subtracting one from a positive number, there is no carry
// out of the result.
if (KnownZero.isNegative())
return Tmp;
}
-
+
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
if (Tmp2 == 1) return 1;
return std::min(Tmp, Tmp2)-1;
break;
-
+
case ISD::SUB:
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
if (Tmp2 == 1) return 1;
-
+
// Handle NEG.
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (CLHS->isNullValue()) {
@@ -2012,15 +2012,15 @@
// sign bits set.
if ((KnownZero | APInt(VTBits, 1)) == Mask)
return VTBits;
-
+
// If the input is known to be positive (the sign bit is known clear),
// the output of the NEG has the same number of sign bits as the input.
if (KnownZero.isNegative())
return Tmp2;
-
+
// Otherwise, we treat this like a SUB.
}
-
+
// Sub can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
@@ -2032,7 +2032,7 @@
// case for targets like X86.
break;
}
-
+
// Handle LOADX separately here. EXTLOAD case will fallthrough.
if (Op.getOpcode() == ISD::LOAD) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
@@ -2050,19 +2050,19 @@
// Allow the target to implement this method for its nodes.
if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
- Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_VOID) {
unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth);
if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits);
}
-
+
// Finally, if we can prove that the top bits of the result are 0's or 1's,
// use this information.
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VTBits);
ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
-
+
if (KnownZero.isNegative()) { // sign bit is 0
Mask = KnownZero;
} else if (KnownOne.isNegative()) { // sign bit is 1;
@@ -2071,7 +2071,7 @@
// Nothing known.
return FirstAnswer;
}
-
+
// Okay, we know that the sign bit in Mask is set. Use CLZ to determine
// the number of identical bits in the top of the input value.
Mask = ~Mask;
@@ -2135,7 +2135,7 @@
SDNode *N = NodeAllocator.Allocate<SDNode>();
new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT));
CSEMap.InsertNode(N, IP);
-
+
AllNodes.push_back(N);
#ifndef NDEBUG
VerifyNode(N);
@@ -2164,7 +2164,7 @@
if (VT==MVT::ppcf128)
break;
APFloat apf = APFloat(APInt(BitWidth, 2, zero));
- (void)apf.convertFromAPInt(Val,
+ (void)apf.convertFromAPInt(Val,
Opcode==ISD::SINT_TO_FP,
APFloat::rmNearestTiesToEven);
return getConstantFP(apf, VT);
@@ -2259,7 +2259,7 @@
assert(Operand.getValueType().bitsLT(VT)
&& "Invalid zext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
- return getNode(ISD::ZERO_EXTEND, DL, VT,
+ return getNode(ISD::ZERO_EXTEND, DL, VT,
Operand.getNode()->getOperand(0));
break;
case ISD::ANY_EXTEND:
@@ -2536,7 +2536,7 @@
// EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
if (N1.getOpcode() == ISD::UNDEF)
return getUNDEF(VT);
-
+
// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
// expanding copies of large vectors from registers.
if (N2C &&
@@ -2554,7 +2554,7 @@
// expanding large vector constants.
if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR)
return N1.getOperand(N2C->getZExtValue());
-
+
// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
// operations are lowered to scalars.
if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
@@ -2576,7 +2576,7 @@
// EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
// 64-bit integers into 32-bit parts. Instead of building the extract of
- // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
+ // the BUILD_PAIR, only to have legalize rip it apart, just do it now.
if (N1.getOpcode() == ISD::BUILD_PAIR)
return N1.getOperand(N2C->getZExtValue());
@@ -2618,12 +2618,12 @@
APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
APFloat::opStatus s;
switch (Opcode) {
- case ISD::FADD:
+ case ISD::FADD:
s = V1.add(V2, APFloat::rmNearestTiesToEven);
if (s != APFloat::opInvalidOp)
return getConstantFP(V1, VT);
break;
- case ISD::FSUB:
+ case ISD::FSUB:
s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
if (s!=APFloat::opInvalidOp)
return getConstantFP(V1, VT);
@@ -2650,7 +2650,7 @@
}
}
}
-
+
// Canonicalize an UNDEF to the RHS, even over a constant.
if (N1.getOpcode() == ISD::UNDEF) {
if (isCommutativeBinOp(Opcode)) {
@@ -2679,8 +2679,8 @@
}
}
}
-
- // Fold a bunch of operators when the RHS is undef.
+
+ // Fold a bunch of operators when the RHS is undef.
if (N2.getOpcode() == ISD::UNDEF) {
switch (Opcode) {
case ISD::XOR:
@@ -2703,7 +2703,7 @@
case ISD::UREM:
case ISD::SREM:
return N2; // fold op(arg1, undef) -> undef
- case ISD::MUL:
+ case ISD::MUL:
case ISD::AND:
case ISD::SRL:
case ISD::SHL:
@@ -2905,7 +2905,7 @@
return DAG.getConstant(Val, VT);
}
-/// getMemBasePlusOffset - Returns base and offset node for the
+/// getMemBasePlusOffset - Returns base and offset node for the
///
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
@@ -3330,7 +3330,7 @@
SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
SDValue Chain,
- SDValue Ptr, SDValue Cmp,
+ SDValue Ptr, SDValue Cmp,
SDValue Swp, const Value* PtrVal,
unsigned Alignment) {
assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
@@ -3359,7 +3359,7 @@
SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
SDValue Chain,
- SDValue Ptr, SDValue Val,
+ SDValue Ptr, SDValue Val,
const Value* PtrVal,
unsigned Alignment) {
assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
@@ -3368,9 +3368,9 @@
Opcode == ISD::ATOMIC_LOAD_OR ||
Opcode == ISD::ATOMIC_LOAD_XOR ||
Opcode == ISD::ATOMIC_LOAD_NAND ||
- Opcode == ISD::ATOMIC_LOAD_MIN ||
+ Opcode == ISD::ATOMIC_LOAD_MIN ||
Opcode == ISD::ATOMIC_LOAD_MAX ||
- Opcode == ISD::ATOMIC_LOAD_UMIN ||
+ Opcode == ISD::ATOMIC_LOAD_UMIN ||
Opcode == ISD::ATOMIC_LOAD_UMAX ||
Opcode == ISD::ATOMIC_SWAP) &&
"Invalid Atomic Op");
@@ -3407,7 +3407,7 @@
VTs.reserve(NumOps);
for (unsigned i = 0; i < NumOps; ++i)
VTs.push_back(Ops[i].getValueType());
- return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
+ return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
Ops, NumOps);
}
@@ -3437,7 +3437,7 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDValue(E, 0);
-
+
N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
@@ -3477,7 +3477,7 @@
}
SDValue
-SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, MVT EVT,
@@ -3675,7 +3675,7 @@
case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
default: break;
}
-
+
switch (Opcode) {
default: break;
case ISD::SELECT_CC: {
@@ -3736,8 +3736,8 @@
if (NumVTs == 1)
return getNode(Opcode, DL, VTs[0], Ops, NumOps);
return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
-}
-
+}
+
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
if (VTList.NumVTs == 1)
@@ -3910,7 +3910,7 @@
E = VTList.rend(); I != E; ++I) {
if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1])
continue;
-
+
bool NoMatch = false;
for (unsigned i = 2; i != NumVTs; ++i)
if (VTs[i] != I->VTs[i]) {
@@ -3920,7 +3920,7 @@
if (!NoMatch)
return *I;
}
-
+
MVT *Array = Allocator.Allocate<MVT>(NumVTs);
std::copy(VTs, VTs+NumVTs, Array);
SDVTList Result = makeVTList(Array, NumVTs);
@@ -3938,23 +3938,23 @@
SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
SDNode *N = InN.getNode();
assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
-
+
// Check to see if there is no change.
if (Op == N->getOperand(0)) return InN;
-
+
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
return SDValue(Existing, InN.getResNo());
-
+
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
if (!RemoveNodeFromCSEMaps(N))
InsertPos = 0;
-
+
// Now we update the operands.
N->OperandList[0].set(Op);
-
+
// If this gets put into a CSE map, add it.
if (InsertPos) CSEMap.InsertNode(N, InsertPos);
return InN;
@@ -3964,27 +3964,27 @@
UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
SDNode *N = InN.getNode();
assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
-
+
// Check to see if there is no change.
if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
return InN; // No operands changed, just return the input node.
-
+
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
return SDValue(Existing, InN.getResNo());
-
+
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
if (!RemoveNodeFromCSEMaps(N))
InsertPos = 0;
-
+
// Now we update the operands.
if (N->OperandList[0] != Op1)
N->OperandList[0].set(Op1);
if (N->OperandList[1] != Op2)
N->OperandList[1].set(Op2);
-
+
// If this gets put into a CSE map, add it.
if (InsertPos) CSEMap.InsertNode(N, InsertPos);
return InN;
@@ -3997,7 +3997,7 @@
}
SDValue SelectionDAG::
-UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
+UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2,
SDValue Op3, SDValue Op4) {
SDValue Ops[] = { Op1, Op2, Op3, Op4 };
return UpdateNodeOperands(N, Ops, 4);
@@ -4015,7 +4015,7 @@
SDNode *N = InN.getNode();
assert(N->getNumOperands() == NumOps &&
"Update with wrong number of operands");
-
+
// Check to see if there is no change.
bool AnyChange = false;
for (unsigned i = 0; i != NumOps; ++i) {
@@ -4024,20 +4024,20 @@
break;
}
}
-
+
// No operands changed, just return the input node.
if (!AnyChange) return InN;
-
+
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
return SDValue(Existing, InN.getResNo());
-
+
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
if (!RemoveNodeFromCSEMaps(N))
InsertPos = 0;
-
+
// Now we update the operands.
for (unsigned i = 0; i != NumOps; ++i)
if (N->OperandList[i] != Ops[i])
@@ -4125,7 +4125,7 @@
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4133,7 +4133,7 @@
return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4143,7 +4143,7 @@
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2,
- SDValue Op1, SDValue Op2,
+ SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4152,7 +4152,7 @@
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
MVT VT1, MVT VT2, MVT VT3,
- SDValue Op1, SDValue Op2,
+ SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4221,7 +4221,7 @@
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
+SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4229,7 +4229,7 @@
return MorphNodeTo(N, Opc, VTs, Ops, 1);
}
-SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
+SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4239,7 +4239,7 @@
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
MVT VT1, MVT VT2,
- SDValue Op1, SDValue Op2,
+ SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4277,7 +4277,7 @@
N->NodeType = Opc;
N->ValueList = VTs.VTs;
N->NumValues = VTs.NumVTs;
-
+
// Clear the operands list, updating used nodes to remove this from their
// use list. Keep track of any operands that become dead as a result.
SmallPtrSet<SDNode*, 16> DeadNodeSet;
@@ -4306,7 +4306,7 @@
N->OperandsNeedDelete = true;
}
}
-
+
// Assign the new operands.
N->NumOperands = NumOps;
for (unsigned i = 0, e = NumOps; i != e; ++i) {
@@ -4360,7 +4360,7 @@
return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
SDValue Op;
@@ -4389,7 +4389,7 @@
return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2,
const SDValue *Ops, unsigned NumOps) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
@@ -4462,7 +4462,7 @@
void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
DAGUpdateListener *UpdateListener) {
SDNode *From = FromN.getNode();
- assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
+ assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
"Cannot replace with this method!");
assert(From != To.getNode() && "Cannot replace uses of with self");
@@ -4665,7 +4665,7 @@
for (unsigned i = 0; i != Num; ++i) {
unsigned FromResNo = From[i].getResNo();
SDNode *FromNode = From[i].getNode();
- for (SDNode::use_iterator UI = FromNode->use_begin(),
+ for (SDNode::use_iterator UI = FromNode->use_begin(),
E = FromNode->use_end(); UI != E; ++UI) {
SDUse &Use = UI.getUse();
if (Use.getResNo() == FromResNo) {
@@ -4810,7 +4810,7 @@
assert(isVolatile() == vol && "Volatile representation error!");
}
-MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
+MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops,
unsigned NumOps, MVT memvt, const Value *srcValue,
int SVO, unsigned alignment, bool vol)
@@ -4842,9 +4842,9 @@
int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
-
+
// Check if the memory reference references a frame index
- const FrameIndexSDNode *FI =
+ const FrameIndexSDNode *FI =
dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
if (!getSrcValue() && FI)
return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
@@ -4938,18 +4938,18 @@
}
/// reachesChainWithoutSideEffects - Return true if this operand (which must
-/// be a chain) reaches the specified operand without crossing any
+/// be a chain) reaches the specified operand without crossing any
/// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
-bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
+bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth) const {
if (*this == Dest) return true;
-
+
// Don't search too deeply, we just want to be able to see through
// TokenFactor's etc.
if (Depth == 0) return false;
-
+
// If this is a token factor, all inputs to the TF happen in parallel. If any
// of the operands of the TF reach dest, then we can do the xform.
if (getOpcode() == ISD::TokenFactor) {
@@ -4958,7 +4958,7 @@
return true;
return false;
}
-
+
// Loads don't have side effects, look through them.
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
if (!Ld->isVolatile())
@@ -5018,7 +5018,7 @@
return "<<Unknown Target Node>>";
}
return "<<Unknown Node>>";
-
+
#ifndef NDEBUG
case ISD::DELETED_NODE:
return "<<Deleted Node!>>";
@@ -5097,7 +5097,7 @@
case ISD::HANDLENODE: return "handlenode";
case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
case ISD::CALL: return "call";
-
+
// Unary operators
case ISD::FABS: return "fabs";
case ISD::FNEG: return "fneg";
@@ -5166,10 +5166,10 @@
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
-
+
case ISD::EXTRACT_SUBREG: return "extract_subreg";
case ISD::INSERT_SUBREG: return "insert_subreg";
-
+
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";
@@ -5186,7 +5186,7 @@
case ISD::FP_TO_SINT: return "fp_to_sint";
case ISD::FP_TO_UINT: return "fp_to_uint";
case ISD::BIT_CONVERT: return "bit_convert";
-
+
case ISD::CONVERT_RNDSAT: {
switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
default: assert(0 && "Unknown cvt code!");
@@ -5494,7 +5494,7 @@
void SelectionDAG::dump() const {
cerr << "SelectionDAG has " << AllNodes.size() << " nodes:";
-
+
for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
I != E; ++I) {
const SDNode *N = I;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Feb 17 16:15:04 2009
@@ -338,7 +338,7 @@
unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
CU.getFilename());
unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
- SPI->getLine(),
+ SPI->getLine(),
SPI->getColumn());
DL = DebugLoc::get(idx);
}
@@ -360,7 +360,7 @@
DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
}
}
-
+
break;
}
}
@@ -463,7 +463,7 @@
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
- Hi = getCopyFromParts(DAG, dl,
+ Hi = getCopyFromParts(DAG, dl,
Parts+RoundParts, OddParts, PartVT, OddVT);
// Combine the round and odd parts.
@@ -646,7 +646,7 @@
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
- Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
+ Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
@@ -656,17 +656,17 @@
SDValue &Part0 = Parts[i];
SDValue &Part1 = Parts[i+StepSize/2];
- Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
+ Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
ThisVT, Part0,
DAG.getConstant(1, PtrVT));
- Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
+ Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
ThisVT, Part0,
DAG.getConstant(0, PtrVT));
if (ThisBits == PartBits && ThisVT != PartVT) {
- Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
+ Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
PartVT, Part0);
- Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
+ Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
PartVT, Part1);
}
}
@@ -687,7 +687,7 @@
assert(ValueVT.getVectorElementType() == PartVT &&
ValueVT.getVectorNumElements() == 1 &&
"Only trivial vector-to-scalar conversions should get here!");
- Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+ Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
PartVT, Val,
DAG.getConstant(0, PtrVT));
}
@@ -713,12 +713,12 @@
SmallVector<SDValue, 8> Ops(NumIntermediates);
for (unsigned i = 0; i != NumIntermediates; ++i)
if (IntermediateVT.isVector())
- Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
+ Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
IntermediateVT, Val,
DAG.getConstant(i * (NumElements / NumIntermediates),
PtrVT));
else
- Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+ Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
IntermediateVT, Val,
DAG.getConstant(i, PtrVT));
@@ -935,7 +935,7 @@
}
// Create a BUILD_VECTOR node.
- return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
VT, &Ops[0], Ops.size());
}
@@ -959,7 +959,7 @@
void SelectionDAGLowering::visitRet(ReturnInst &I) {
if (I.getNumOperands() == 0) {
- DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
MVT::Other, getControlRoot()));
return;
}
@@ -1250,7 +1250,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
@@ -1344,7 +1344,7 @@
MVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
@@ -1401,7 +1401,7 @@
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
- DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
MVT::Other, Index.getValue(1),
Table, Index));
}
@@ -1424,10 +1424,10 @@
// This value may be smaller or larger than the target's pointer type, and
// therefore require extension or truncating.
if (VT.bitsGT(TLI.getPointerTy()))
- SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
else
- SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
@@ -1478,10 +1478,10 @@
SDValue ShiftOp;
if (VT.bitsGT(TLI.getPointerTy()))
- ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
else
- ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), SUB);
B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
@@ -1518,13 +1518,13 @@
// Make desired shift
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
TLI.getPointerTy());
- SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
+ SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
TLI.getPointerTy(),
DAG.getConstant(1, TLI.getPointerTy()),
ShiftOp);
// Emit bit tests and jumps
- SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
+ SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
TLI.getPointerTy(), SwitchVal,
DAG.getConstant(B.Mask, TLI.getPointerTy()));
SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
@@ -1577,7 +1577,7 @@
CurMBB->addSuccessor(LandingPad);
// Drop into normal successor.
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
MVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -2144,7 +2144,7 @@
Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
if (CV == CNZ) {
SDValue Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Op2.getValueType(), Op2));
return;
}
@@ -2155,7 +2155,7 @@
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
SDValue Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Op2.getValueType(), Op2));
return;
}
@@ -2168,7 +2168,7 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
Op1.getValueType(), Op1, Op2));
}
@@ -2177,14 +2177,14 @@
SDValue Op2 = getValue(I.getOperand(1));
if (!isa<VectorType>(I.getType())) {
if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
- Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(), Op2);
else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
- Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
+ Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(), Op2);
}
- setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
Op1.getValueType(), Op1, Op2));
}
@@ -2221,7 +2221,7 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
+ setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
Op1, Op2, Opcode));
}
@@ -2250,12 +2250,12 @@
SDValue FalseVal = getValue(I.getOperand(2));
for (unsigned i = 0; i != NumValues; ++i)
- Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
+ Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
TrueVal.getValueType(), Cond,
SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@@ -2289,7 +2289,7 @@
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
DestVT, N, DAG.getIntPtrConstant(0)));
}
@@ -2353,7 +2353,7 @@
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
- setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
DestVT, N));
}
@@ -2364,7 +2364,7 @@
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
if (DestVT != N.getValueType())
- setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
DestVT, N)); // convert types
else
setValue(&I, N); // noop cast.
@@ -2373,18 +2373,18 @@
void SelectionDAGLowering::visitInsertElement(User &I) {
SDValue InVec = getValue(I.getOperand(0));
SDValue InVal = getValue(I.getOperand(1));
- SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(2)));
- setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
TLI.getValueType(I.getType()),
InVec, InVal, InIdx));
}
void SelectionDAGLowering::visitExtractElement(User &I) {
SDValue InVec = getValue(I.getOperand(0));
- SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
TLI.getPointerTy(),
getValue(I.getOperand(1)));
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
@@ -2417,7 +2417,7 @@
int SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
- setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@@ -2431,7 +2431,7 @@
// lengths match.
if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
// The shuffle is concatenating two vectors together.
- setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, Src1, Src2));
return;
}
@@ -2448,9 +2448,9 @@
MOps1[i] = UndefVal;
MOps2[i] = UndefVal;
}
- Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
+ Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, MOps1, NumConcat);
- Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
+ Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
VT, MOps2, NumConcat);
delete [] MOps1;
@@ -2470,11 +2470,11 @@
MaskEltVT));
}
}
- Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask.getValueType(),
&MappedOps[0], MappedOps.size());
- setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@@ -2570,10 +2570,10 @@
}
}
}
- Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Mask.getValueType(),
&MappedOps[0], MappedOps.size());
- setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
VT, Src1, Src2, Mask));
return;
}
@@ -2597,11 +2597,11 @@
EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
else
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
- EltVT, Src2,
+ EltVT, Src2,
DAG.getConstant(Idx - SrcNumElts, PtrVT)));
}
}
- setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
VT, &Ops[0], Ops.size()));
}
@@ -2641,7 +2641,7 @@
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&AggValueVTs[0], NumAggValues),
&Values[0], NumAggValues));
}
@@ -2669,7 +2669,7 @@
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValValueVTs[0], NumValValues),
&Values[0], NumValValues));
}
@@ -2719,10 +2719,10 @@
// If the index is smaller or larger than intptr_t, truncate or extend
// it.
if (IdxN.getValueType().bitsLT(N.getValueType()))
- IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
N.getValueType(), IdxN);
else if (IdxN.getValueType().bitsGT(N.getValueType()))
- IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
N.getValueType(), IdxN);
// If this is a multiply by a power of two, turn it into a shl
@@ -2730,17 +2730,17 @@
if (ElementSize != 1) {
if (isPowerOf2_64(ElementSize)) {
unsigned Amt = Log2_64(ElementSize);
- IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
N.getValueType(), IdxN,
DAG.getConstant(Amt, TLI.getPointerTy()));
} else {
SDValue Scale = DAG.getIntPtrConstant(ElementSize);
- IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
+ IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
N.getValueType(), IdxN, Scale);
}
}
- N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
N.getValueType(), N, IdxN);
}
}
@@ -2762,10 +2762,10 @@
SDValue AllocSize = getValue(I.getArraySize());
MVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
- AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IntPtr, AllocSize);
else if (IntPtr.bitsGT(AllocSize.getValueType()))
- AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
IntPtr, AllocSize);
AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
@@ -2781,18 +2781,18 @@
// Round the size of the allocation up to the stack alignment size
// by add SA-1 to the size.
- AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(StackAlign-1));
// Mask out the low bits for alignment purposes.
- AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
+ AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
AllocSize.getValueType(), AllocSize,
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
MVT::Other);
- SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
+ SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, 2, Ops, 3);
setValue(&I, DSA);
DAG.setRoot(DSA.getValue(1));
@@ -2836,7 +2836,7 @@
MVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
- DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ DAG.getNode(ISD::ADD, getCurDebugLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
SV, Offsets[i],
@@ -2846,7 +2846,7 @@
}
if (!ConstantMemory) {
- SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other,
&Chains[0], NumValues);
if (isVolatile)
@@ -2855,7 +2855,7 @@
PendingLoads.push_back(Chain);
}
- setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
@@ -2886,13 +2886,13 @@
for (unsigned i = 0; i != NumValues; ++i)
Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
SDValue(Src.getNode(), Src.getResNo() + i),
- DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ DAG.getNode(ISD::ADD, getCurDebugLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
PtrV, Offsets[i],
isVolatile, Alignment);
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other, &Chains[0], NumValues));
}
@@ -2961,15 +2961,15 @@
Info.readMem, Info.writeMem);
}
else if (!HasChain)
- Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
else if (I.getType() != Type::VoidTy)
- Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
else
- Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
+ Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
VTList, VTs.size(),
&Ops[0], Ops.size());
@@ -3121,7 +3121,7 @@
MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
SDValue Ops[] = { Op1, Op2 };
- SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
+ SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
setValue(&I, Result);
@@ -3235,7 +3235,7 @@
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::i32, t13);
// Add the exponent into the result in integer domain.
@@ -3291,7 +3291,7 @@
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@@ -3317,7 +3317,7 @@
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@@ -3351,7 +3351,7 @@
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
@@ -3399,7 +3399,7 @@
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@@ -3425,7 +3425,7 @@
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@@ -3460,7 +3460,7 @@
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
@@ -3510,7 +3510,7 @@
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@@ -3532,7 +3532,7 @@
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@@ -3562,7 +3562,7 @@
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
- result = DAG.getNode(ISD::FADD, dl,
+ result = DAG.getNode(ISD::FADD, dl,
MVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
@@ -3615,7 +3615,7 @@
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl,
+ result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
@@ -3640,7 +3640,7 @@
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl,
+ result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@@ -3676,7 +3676,7 @@
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl,
+ result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
}
} else {
@@ -3773,7 +3773,7 @@
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl,
+ result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
@@ -3809,7 +3809,7 @@
SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl,
+ result = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f32, TwoToFractionalPartOfX);
}
} else {
@@ -3903,7 +3903,7 @@
unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
unsigned idx = DAG.getMachineFunction().
getOrCreateDebugLocID(SrcFile,
- SPI.getLine(),
+ SPI.getLine(),
SPI.getColumn());
setCurDebugLoc(DebugLoc::get(idx));
}
@@ -4477,7 +4477,7 @@
I.getType() == I.getOperand(2)->getType()) {
SDValue LHS = getValue(I.getOperand(1));
SDValue RHS = getValue(I.getOperand(2));
- setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
LHS.getValueType(), LHS, RHS));
return;
}
@@ -4489,7 +4489,7 @@
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@@ -4501,7 +4501,7 @@
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@@ -4513,7 +4513,7 @@
I.getOperand(1)->getType()->isFloatingPoint() &&
I.getType() == I.getOperand(1)->getType()) {
SDValue Tmp = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
+ setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
@@ -4606,7 +4606,7 @@
Parts[i] = P;
}
- Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
+ Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
NumRegs, RegisterVT, ValueVT);
Part += NumRegs;
Parts.clear();
@@ -5370,7 +5370,7 @@
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
if (!RetValRegs.Regs.empty()) {
- SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
+ SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
Chain, &Flag);
// FIXME: Why don't we do this for inline asms with MRVs?
@@ -5817,7 +5817,7 @@
ComputeValueVTs(TLI, AI->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (!AI->use_empty()) {
- SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
+ SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
SDL->getCurDebugLoc()));
// If this argument is live outside of the entry block, insert a copy from
// whereever we got it to the vreg that other BB's will reference it as.
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 17 16:15:04 2009
@@ -34,30 +34,30 @@
#include "llvm/Support/CommandLine.h"
using namespace llvm;
-static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
+static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
cl::desc("enable preincrement load/store generation on PPC (experimental)"),
cl::Hidden);
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
-
+
setPow2DivIsCheap();
// Use _setjmp/_longjmp instead of setjmp/longjmp.
setUseUnderscoreSetJmp(true);
setUseUnderscoreLongJmp(true);
-
+
// Set up the register classes.
addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
-
+
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-
+
// PowerPC has pre-inc load and store's.
setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
@@ -92,7 +92,7 @@
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
-
+
// We don't support sin/cos/sqrt/fmod/pow
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
@@ -104,16 +104,16 @@
setOperationAction(ISD::FPOW , MVT::f32, Expand);
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
-
+
// If we're enabling GP optimizations, use hardware square root
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
}
-
+
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
-
+
// PowerPC does not have BSWAP, CTPOP or CTTZ
setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
@@ -121,29 +121,29 @@
setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
-
+
// PowerPC does not have ROTR
setOperationAction(ISD::ROTR, MVT::i32 , Expand);
setOperationAction(ISD::ROTR, MVT::i64 , Expand);
-
+
// PowerPC does not have Select
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::i64, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f64, Expand);
-
+
// PowerPC wants to turn select_cc of FP into fsel when possible.
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// PowerPC wants to optimize integer setcc a bit
setOperationAction(ISD::SETCC, MVT::i32, Custom);
-
+
// PowerPC does not have BRCOND which requires SetCC
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
-
+
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
@@ -162,14 +162,14 @@
// Support label based line numbers.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
-
+
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
-
-
- // We want to legalize GlobalAddress and ConstantPool nodes into the
+
+
+ // We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
@@ -179,7 +179,7 @@
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
-
+
// RET must be custom lowered, to meet ABI requirements.
setOperationAction(ISD::RET , MVT::Other, Custom);
@@ -191,24 +191,24 @@
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
-
+
// VAARG is custom lowered with ELF 32 ABI
if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
setOperationAction(ISD::VAARG, MVT::Other, Custom);
else
setOperationAction(ISD::VAARG, MVT::Other, Expand);
-
+
// Use the default implementation.
setOperationAction(ISD::VACOPY , MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
-
+
// Comparisons that require checking two conditions.
setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
@@ -222,7 +222,7 @@
setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
-
+
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
@@ -230,12 +230,12 @@
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
-
+
// FIXME: disable this lowered code. This generates 64-bit register values,
// and we don't model the fact that the top part is clobbered by calls. We
// need to flag these together so that the value isn't live across a call.
//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
-
+
// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
} else {
@@ -269,7 +269,7 @@
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , VT, Legal);
setOperationAction(ISD::SUB , VT, Legal);
-
+
// We promote all shuffles to v16i8.
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
@@ -287,7 +287,7 @@
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
-
+
// No other operations are legal.
setOperationAction(ISD::MUL , VT, Expand);
setOperationAction(ISD::SDIV, VT, Expand);
@@ -320,12 +320,12 @@
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
-
+
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
-
+
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
setOperationAction(ISD::MUL, MVT::v4i32, Custom);
setOperationAction(ISD::MUL, MVT::v8i16, Custom);
@@ -333,16 +333,16 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
-
+
setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
-
+
setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrOneBooleanContent);
-
+
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
setStackPointerRegisterToSaveRestore(PPC::X1);
setExceptionPointerRegister(PPC::X3);
@@ -352,13 +352,13 @@
setExceptionPointerRegister(PPC::R3);
setExceptionSelectorRegister(PPC::R4);
}
-
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
setTargetDAGCombine(ISD::STORE);
setTargetDAGCombine(ISD::BR_CC);
setTargetDAGCombine(ISD::BSWAP);
-
+
// Darwin long double math library functions have $LDBL128 appended.
if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
@@ -457,7 +457,7 @@
/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
/// true if Op is undef or if it matches the specified value.
static bool isConstantOrUndef(SDValue Op, unsigned Val) {
- return Op.getOpcode() == ISD::UNDEF ||
+ return Op.getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(Op)->getZExtValue() == Val;
}
@@ -498,13 +498,13 @@
/// isVMerge - Common function, used to match vmrg* shuffles.
///
-static bool isVMerge(SDNode *N, unsigned UnitSize,
+static bool isVMerge(SDNode *N, unsigned UnitSize,
unsigned LHSStart, unsigned RHSStart) {
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!");
-
+
for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
@@ -542,9 +542,9 @@
unsigned i;
for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
/*search*/;
-
+
if (i == 16) return -1; // all undef.
-
+
// Otherwise, check to see if the rest of the elements are consequtively
// numbered from this value.
unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
@@ -562,7 +562,7 @@
if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
return -1;
}
-
+
return ShiftAmt;
}
@@ -573,7 +573,7 @@
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
N->getNumOperands() == 16 &&
(EltSize == 1 || EltSize == 2 || EltSize == 4));
-
+
// This is a splat operation if each element of the permute is the same, and
// if the value doesn't reference the second vector.
unsigned ElementBase = 0;
@@ -585,14 +585,14 @@
if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
return false;
-
+
// Check that they are consequtive.
for (unsigned i = 1; i != EltSize; ++i) {
if (!isa<ConstantSDNode>(N->getOperand(i)) ||
cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
return false;
}
-
+
assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
@@ -639,31 +639,31 @@
unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
SDValue UniquedVals[4];
assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
-
+
// See if all of the elements in the buildvector agree across.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
// If the element isn't a constant, bail fully out.
if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
-
+
if (UniquedVals[i&(Multiple-1)].getNode() == 0)
UniquedVals[i&(Multiple-1)] = N->getOperand(i);
else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
return SDValue(); // no match.
}
-
+
// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
// either constant or undef values that are identical for each chunk. See
// if these chunks can form into a larger vspltis*.
-
+
// Check to see if all of the leading entries are either 0 or -1. If
// neither, then this won't fit into the immediate field.
bool LeadingZero = true;
bool LeadingOnes = true;
for (unsigned i = 0; i != Multiple-1; ++i) {
if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
-
+
LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
}
@@ -682,10 +682,10 @@
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
return DAG.getTargetConstant(Val, MVT::i32);
}
-
+
return SDValue();
}
-
+
// Check to see if this buildvec has a single non-undef value in its elements.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
@@ -694,9 +694,9 @@
else if (OpVal != N->getOperand(i))
return SDValue();
}
-
+
if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
-
+
unsigned ValSizeInBytes = 0;
uint64_t Value = 0;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
@@ -712,13 +712,13 @@
// this splat. The only case that we could fit the replicated bits into our
// immediate field for would be zero, and we prefer to use vxor for it.
if (ValSizeInBytes < ByteSize) return SDValue();
-
+
// If the element value is larger than the splat value, cut it in half and
// check to see if the two halves are equal. Continue doing this until we
// get to ByteSize. This allows us to handle 0x01010101 as 0x01.
while (ValSizeInBytes > ByteSize) {
ValSizeInBytes >>= 1;
-
+
// If the top half equals the bottom half, we're still ok.
if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
(Value & ((1 << (8*ValSizeInBytes))-1)))
@@ -728,7 +728,7 @@
// Properly sign extend the value.
int ShAmt = (4-ByteSize)*8;
int MaskVal = ((int)Value << ShAmt) >> ShAmt;
-
+
// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
if (MaskVal == 0) return SDValue();
@@ -749,7 +749,7 @@
static bool isIntS16Immediate(SDNode *N, short &Imm) {
if (N->getOpcode() != ISD::Constant)
return false;
-
+
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
@@ -773,14 +773,14 @@
return false; // r+i
if (N.getOperand(1).getOpcode() == PPCISD::Lo)
return false; // r+i
-
+
Base = N.getOperand(0);
Index = N.getOperand(1);
return true;
} else if (N.getOpcode() == ISD::OR) {
if (isIntS16Immediate(N.getOperand(1), imm))
return false; // r+i can fold it if we can.
-
+
// If this is an or of disjoint bitfields, we can codegen this as an add
// (for better address arithmetic) if the LHS and RHS of the OR are provably
// disjoint.
@@ -790,7 +790,7 @@
APInt::getAllOnesValue(N.getOperand(0)
.getValueSizeInBits()),
LHSKnownZero, LHSKnownOne);
-
+
if (LHSKnownZero.getBoolValue()) {
DAG.ComputeMaskedBits(N.getOperand(1),
APInt::getAllOnesValue(N.getOperand(1)
@@ -805,7 +805,7 @@
}
}
}
-
+
return false;
}
@@ -820,7 +820,7 @@
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
-
+
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm)) {
@@ -864,7 +864,7 @@
}
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
// Loading from a constant address.
-
+
// If this address fits entirely in a 16-bit sext immediate field, codegen
// this as "d, 0"
short Imm;
@@ -878,17 +878,17 @@
if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
-
+
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
-
+
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
return true;
}
}
-
+
Disp = DAG.getTargetConstant(0, getPointerTy());
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
@@ -907,7 +907,7 @@
// reg+imm, e.g. where imm = 0.
if (SelectAddressRegReg(N, Base, Index, DAG))
return true;
-
+
// If the operand is an addition, always emit this as [r+r], since this is
// better (for code size, and execution, as the memop does the add for free)
// than emitting an explicit add.
@@ -916,7 +916,7 @@
Index = N.getOperand(1);
return true;
}
-
+
// Otherwise, do it the hard way, using R0 as the base register.
Base = DAG.getRegister(PPC::R0, N.getValueType());
Index = N;
@@ -934,7 +934,7 @@
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
-
+
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
@@ -986,12 +986,12 @@
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
return true;
}
-
+
// Fold the low-part of 32-bit absolute addresses into addr mode.
if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
-
+
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
@@ -1001,7 +1001,7 @@
}
}
}
-
+
Disp = DAG.getTargetConstant(0, getPointerTy());
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
@@ -1020,13 +1020,13 @@
SelectionDAG &DAG) const {
// Disabled by default for now.
if (!EnablePPCPreinc) return false;
-
+
SDValue Ptr;
MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
VT = LD->getMemoryVT();
-
+
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ST = ST;
Ptr = ST->getBasePtr();
@@ -1037,9 +1037,9 @@
// PowerPC doesn't have preinc load/store instructions for vectors.
if (VT.isVector())
return false;
-
+
// TODO: Check reg+reg first.
-
+
// LDU/STU use reg+imm*4, others use reg+imm.
if (VT != MVT::i64) {
// reg + imm
@@ -1058,8 +1058,8 @@
LD->getExtensionType() == ISD::SEXTLOAD &&
isa<ConstantSDNode>(Offset))
return false;
- }
-
+ }
+
AM = ISD::PRE_INC;
return true;
}
@@ -1068,7 +1068,7 @@
// LowerOperation implementation
//===----------------------------------------------------------------------===//
-SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
+SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
@@ -1079,7 +1079,7 @@
DebugLoc dl = Op.getDebugLoc();
const TargetMachine &TM = DAG.getTarget();
-
+
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
@@ -1091,14 +1091,14 @@
// The address of the global is just (hi(&g)+lo(&g)).
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
-
+
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg,
+ DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
-
+
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
return Lo;
}
@@ -1110,7 +1110,7 @@
SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there isn't really any debug loc here
DebugLoc dl = Op.getDebugLoc();
-
+
const TargetMachine &TM = DAG.getTarget();
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
@@ -1124,25 +1124,25 @@
// The address of the global is just (hi(&g)+lo(&g)).
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
-
+
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg,
+ DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
-
+
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
return Lo;
}
-SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
+SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) {
assert(0 && "TLS not implemented for PPC.");
return SDValue(); // Not reached
}
-SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
+SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
@@ -1151,7 +1151,7 @@
SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there isn't really any debug info here
DebugLoc dl = GSDN->getDebugLoc();
-
+
const TargetMachine &TM = DAG.getTarget();
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
@@ -1165,19 +1165,19 @@
// The address of the global is just (hi(&g)+lo(&g)).
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
-
+
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg,
+ DAG.getNode(PPCISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
-
+
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
-
+
if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
return Lo;
-
+
// If the global is weak or external, we have to go through the lazy
// resolution stub.
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
@@ -1186,7 +1186,7 @@
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
DebugLoc dl = Op.getDebugLoc();
-
+
// If we're comparing for equality to zero, expose the fact that this is
// implented as a ctlz/srl pair on ppc, so that the dag combiner can
// fold the new nodes.
@@ -1197,20 +1197,20 @@
if (VT.bitsLT(MVT::i32)) {
VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
- }
+ }
unsigned Log2b = Log2_32(VT.getSizeInBits());
SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
DAG.getConstant(Log2b, MVT::i32));
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
}
- // Leave comparisons against 0 and -1 alone for now, since they're usually
+ // Leave comparisons against 0 and -1 alone for now, since they're usually
// optimized. FIXME: revisit this when we can custom lower all setcc
// optimizations.
if (C->isAllOnesValue() || C->isNullValue())
return SDValue();
}
-
+
// If we have an integer seteq/setne, turn it into a compare against zero
// by xor'ing the rhs with the lhs, which is faster than setting a
// condition register, reading it back out, and masking the correct bit. The
@@ -1219,7 +1219,7 @@
MVT LHSVT = Op.getOperand(0).getValueType();
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT VT = Op.getValueType();
- SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
+ SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
Op.getOperand(1));
return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
}
@@ -1232,7 +1232,7 @@
unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget) {
-
+
assert(0 && "VAARG in ELF32 ABI not implemented yet!");
return SDValue(); // Not reached
}
@@ -1249,7 +1249,7 @@
const Type *IntPtrTy =
DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
- TargetLowering::ArgListTy Args;
+ TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Entry.Ty = IntPtrTy;
@@ -1262,7 +1262,7 @@
Entry.Node = FPtr; Args.push_back(Entry);
Entry.Node = Nest; Args.push_back(Entry);
-
+
// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
@@ -1320,13 +1320,13 @@
SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
-
+
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
-
+
SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
-
+
uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
@@ -1335,22 +1335,22 @@
uint64_t FPROffset = 1;
SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
-
+
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-
+
// Store first byte : number of int regs
SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR,
Op.getOperand(1), SV, 0);
uint64_t nextOffset = FPROffset;
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
ConstFPROffset);
-
+
// Store second byte : number of float regs
SDValue secondStore =
DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset);
nextOffset += StackOffset;
nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
-
+
// Store second word : arguments given on stack
SDValue thirdStore =
DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
@@ -1374,8 +1374,8 @@
};
return FPR;
}
-
-
+
+
static const unsigned FPR[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8
@@ -1397,7 +1397,7 @@
}
SDValue
-PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
+PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
@@ -1413,7 +1413,7 @@
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
DebugLoc dl = Op.getDebugLoc();
-
+
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
bool isMachoABI = Subtarget.isMachoABI();
@@ -1435,9 +1435,9 @@
PPC::X3, PPC::X4, PPC::X5, PPC::X6,
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
};
-
+
static const unsigned *FPR = GetFPR(Subtarget);
-
+
static const unsigned VR[] = {
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
@@ -1448,13 +1448,13 @@
const unsigned Num_VR_Regs = array_lengthof( VR);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
-
+
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
-
+
// In 32-bit non-varargs functions, the stack space for vectors is after the
// stack space for non-vectors. We do not use this space unless we have
// too many vectors to fit in registers, something that only occurs in
- // constructed examples:), but we have to walk the arglist to figure
+ // constructed examples:), but we have to walk the arglist to figure
// that out...for the pathological case, compute VecArgOffset as the
// start of the vector parameter area. Computing VecArgOffset is the
// entire point of the following loop.
@@ -1462,7 +1462,7 @@
// to handle Elf here.
unsigned VecArgOffset = ArgOffset;
if (!isVarArg && !isPPC64) {
- for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
+ for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
++ArgNo) {
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
@@ -1472,7 +1472,7 @@
if (Flags.isByVal()) {
// ObjSize is the true size, ArgSize rounded up to multiple of regs.
ObjSize = Flags.getByValSize();
- unsigned ArgSize =
+ unsigned ArgSize =
((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
VecArgOffset += ArgSize;
continue;
@@ -1505,7 +1505,7 @@
// Add DAG nodes to load the arguments or copy them out of registers. On
// entry to a function on PPC, the arguments start after the linkage area,
// although the first ones are often in registers.
- //
+ //
// In the ELF 32 ABI, GPRs and stack are double word align: an argument
// represented with two words (long long or double) must be copied to an
// even GPR_idx value or to an even ArgOffset value.
@@ -1522,7 +1522,7 @@
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
// See if next argument requires stack alignment in ELF
- bool Align = Flags.isSplit();
+ bool Align = Flags.isSplit();
unsigned CurArgOffset = ArgOffset;
@@ -1566,7 +1566,7 @@
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
- SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
+ SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
@@ -1615,7 +1615,7 @@
ArgSize = PtrByteSize;
}
// Stack align in ELF
- if (needsLoad && Align && isELF32_ABI)
+ if (needsLoad && Align && isELF32_ABI)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
// All int arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
@@ -1649,7 +1649,7 @@
// All int arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += 8;
break;
-
+
case MVT::f32:
case MVT::f64:
// Every 4 bytes of argument space consumes one of the GPRs available for
@@ -1671,7 +1671,7 @@
} else {
needsLoad = true;
}
-
+
// Stack align in ELF
if (needsLoad && Align && isELF32_ABI)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
@@ -1713,7 +1713,7 @@
}
break;
}
-
+
// We need to load the argument to a virtual register if we determined above
// that we ran out of physical registers of the appropriate type.
if (needsLoad) {
@@ -1723,7 +1723,7 @@
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
}
-
+
ArgValues.push_back(ArgVal);
}
@@ -1749,29 +1749,29 @@
// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (isVarArg) {
-
+
int depth;
if (isELF32_ABI) {
VarArgsNumGPR = GPR_idx;
VarArgsNumFPR = FPR_idx;
-
+
// Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
// pointer.
depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
PtrVT.getSizeInBits()/8);
-
+
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
ArgOffset);
}
else
depth = ArgOffset;
-
+
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
depth);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
-
+
// In ELF 32 ABI, the fixed integer arguments of a variadic function are
// stored to the VarArgsFrameIndex on the stack.
if (isELF32_ABI) {
@@ -1832,13 +1832,13 @@
}
}
}
-
+
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, dl,
+ Root = DAG.getNode(ISD::TokenFactor, dl,
MVT::Other, &MemOps[0], MemOps.size());
ArgValues.push_back(Root);
-
+
// Return the new list of results.
return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
@@ -1973,12 +1973,12 @@
static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return 0;
-
+
int Addr = C->getZExtValue();
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
(Addr << 6 >> 6) != Addr)
return 0; // Top 6 bits have to be sext of immediate.
-
+
return DAG.getConstant((int)C->getZExtValue() >> 2,
DAG.getTargetLoweringInfo().getPointerTy()).getNode();
}
@@ -2087,12 +2087,12 @@
}
/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
-/// by "Src" to address "Dst" of size "Size". Alignment information is
+/// by "Src" to address "Dst" of size "Size". Alignment information is
/// specified by the specific parameter attribute. The copy will be passed as
/// a byval function parameter.
/// Sometimes what we are copying is the end of a larger object, the part that
/// does not fit in registers.
-static SDValue
+static SDValue
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
unsigned Size, DebugLoc dl) {
@@ -2139,20 +2139,20 @@
SDValue Callee = TheCall->getCallee();
unsigned NumOps = TheCall->getNumArgs();
DebugLoc dl = TheCall->getDebugLoc();
-
+
bool isMachoABI = Subtarget.isMachoABI();
bool isELF32_ABI = Subtarget.isELF32_ABI();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
unsigned PtrByteSize = isPPC64 ? 8 : 4;
-
+
MachineFunction &MF = DAG.getMachineFunction();
// args_to_use will accumulate outgoing args for the PPCISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDValue> args_to_use;
-
+
// Mark this function as potentially containing a function that contains a
// tail call. As a consequence the frame pointer will be used for dynamicalloc
// and restoring the callers stack pointer in this functions epilog. This is
@@ -2173,12 +2173,12 @@
// Calculate by how many bytes the stack has to be adjusted in case of tail
// call optimization.
int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
-
+
// Adjust the stack pointer for the new arguments...
// These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue CallSeqStart = Chain;
-
+
// Load the return address and frame pointer so it can be move somewhere else
// later.
SDValue LROp, FPOp;
@@ -2192,14 +2192,14 @@
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
-
+
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
// must be stored to our stack, and loaded into integer regs as well, if
// any integer regs are available for argument passing.
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
-
+
static const unsigned GPR_32[] = { // 32-bit registers.
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
@@ -2209,7 +2209,7 @@
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
};
static const unsigned *FPR = GetFPR(Subtarget);
-
+
static const unsigned VR[] = {
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
@@ -2217,7 +2217,7 @@
const unsigned NumGPRs = array_lengthof(GPR_32);
const unsigned NumFPRs = isMachoABI ? 13 : 8;
const unsigned NumVRs = array_lengthof( VR);
-
+
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
std::vector<std::pair<unsigned, SDValue> > RegsToPass;
@@ -2234,7 +2234,7 @@
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
SDValue PtrOff;
-
+
// Stack align in ELF 32
if (isELF32_ABI && Align)
PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
@@ -2261,7 +2261,7 @@
// Everything else is passed left-justified.
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
- SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
NULL, 0, VT);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -2271,7 +2271,7 @@
SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
- CallSeqStart.getNode()->getOperand(0),
+ CallSeqStart.getNode()->getOperand(0),
Flags, DAG, Size, dl);
// This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
@@ -2287,7 +2287,7 @@
// code assumes it is there, even if it could be put entirely into
// registers. (This is not what the doc says.)
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
- CallSeqStart.getNode()->getOperand(0),
+ CallSeqStart.getNode()->getOperand(0),
Flags, DAG, Size, dl);
// This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
@@ -2392,7 +2392,7 @@
case MVT::v16i8:
if (isVarArg) {
// These go aligned on the stack, or in the corresponding R registers
- // when within range. The Darwin PPC ABI doc claims they also go in
+ // when within range. The Darwin PPC ABI doc claims they also go in
// V registers; in fact gcc does this only for arguments that are
// prototyped, not for those that match the ... We do it for all
// arguments, seems to work.
@@ -2403,7 +2403,7 @@
}
// We could elide this store in the case where the object fits
// entirely in R registers. Maybe later.
- PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
@@ -2470,16 +2470,16 @@
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
-
+
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
-
+
// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
if (isVarArg && isELF32_ABI) {
SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
@@ -2517,7 +2517,7 @@
SmallVector<SDValue, 8> Ops;
unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
-
+
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
@@ -2535,7 +2535,7 @@
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2 + (InFlag.getNode() != 0));
InFlag = Chain.getValue(1);
-
+
// Copy the callee address into R12/X12 on darwin.
if (isMachoABI) {
unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
@@ -2566,7 +2566,7 @@
// Add argument registers to the end of the list so that they are known live
// into the call.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
- Ops.push_back(DAG.getRegister(RegsToPass[i].first,
+ Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
// When performing tail call optimization the callee pops its arguments off
@@ -2601,13 +2601,13 @@
unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
-
+
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
CCValAssign &VA = RVLocs[i];
MVT VT = VA.getValVT();
assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyFromReg(Chain, dl,
+ Chain = DAG.getCopyFromReg(Chain, dl,
VA.getLocReg(), VT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
InFlag = Chain.getValue(2);
@@ -2616,7 +2616,7 @@
// If the function returns void, just return the chain.
if (RVLocs.empty())
return Chain;
-
+
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
@@ -2624,7 +2624,7 @@
return Res.getValue(Op.getResNo());
}
-SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
TargetMachine &TM) {
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
@@ -2632,7 +2632,7 @@
DebugLoc dl = Op.getDebugLoc();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
-
+
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
@@ -2672,12 +2672,12 @@
}
SDValue Flag;
-
+
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
Op.getOperand(i*2+1), Flag);
Flag = Chain.getValue(1);
}
@@ -2692,7 +2692,7 @@
const PPCSubtarget &Subtarget) {
// When we pop the dynamic allocation we need to restore the SP link.
DebugLoc dl = Op.getDebugLoc();
-
+
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -2704,13 +2704,13 @@
// Get the operands for the STACKRESTORE.
SDValue Chain = Op.getOperand(0);
SDValue SaveSP = Op.getOperand(1);
-
+
// Load the old link SP.
SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
-
+
// Restore the stack pointer.
Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
-
+
// Store the old link SP.
return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
}
@@ -2757,11 +2757,11 @@
if (!FPSI) {
// Find out what the fix offset of the frame pointer save area.
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
-
+
// Allocate the frame index for frame pointer save area.
- FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
+ FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
// Save the result.
- FI->setFramePointerSaveIndex(FPSI);
+ FI->setFramePointerSaveIndex(FPSI);
}
return DAG.getFrameIndex(FPSI, PtrVT);
}
@@ -2772,8 +2772,8 @@
// Get the inputs.
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
- DebugLoc dl = Op.getDebugLoc();
-
+ DebugLoc dl = Op.getDebugLoc();
+
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Negate the size.
@@ -2794,18 +2794,18 @@
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
!Op.getOperand(2).getValueType().isFloatingPoint())
return SDValue();
-
+
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
-
+
// Cannot handle SETEQ/SETNE.
if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
-
+
MVT ResVT = Op.getValueType();
MVT CmpVT = Op.getOperand(0).getValueType();
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
DebugLoc dl = Op.getDebugLoc();
-
+
// If the RHS of the comparison is a 0.0, we don't need to do the
// subtraction at all.
if (isFloatingPointZero(RHS))
@@ -2829,7 +2829,7 @@
return DAG.getNode(PPCISD::FSEL, dl, ResVT,
DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
}
-
+
SDValue Cmp;
switch (CC) {
default: break; // SETUO etc aren't handled by fsel.
@@ -2901,15 +2901,15 @@
return SDValue();
if (Op.getOperand(0).getValueType() == MVT::i64) {
- SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
+ SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
if (Op.getValueType() == MVT::f32)
- FP = DAG.getNode(ISD::FP_ROUND, dl,
+ FP = DAG.getNode(ISD::FP_ROUND, dl,
MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
-
+
assert(Op.getOperand(0).getValueType() == MVT::i32 &&
"Unhandled SINT_TO_FP type in custom expander!");
// Since we only generate this in 64-bit mode, we can take advantage of
@@ -2920,10 +2920,10 @@
int FrameIdx = FrameInfo->CreateStackObject(8, 8);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
-
+
SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
Op.getOperand(0));
-
+
// STD the extended value into the stack slot.
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
@@ -2932,7 +2932,7 @@
DAG.getMemOperand(MO));
// Load the value as a double.
SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
-
+
// FCFID it and return it.
SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
if (Op.getValueType() == MVT::f32)
@@ -3009,14 +3009,14 @@
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SHL!");
-
+
// Expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
SDValue Lo = Op.getOperand(0);
SDValue Hi = Op.getOperand(1);
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
-
+
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
@@ -3038,14 +3038,14 @@
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRL!");
-
+
// Expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
SDValue Lo = Op.getOperand(0);
SDValue Hi = Op.getOperand(1);
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
-
+
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
@@ -3067,13 +3067,13 @@
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRA!");
-
+
// Expand into a bunch of logical ops, followed by a select_cc.
SDValue Lo = Op.getOperand(0);
SDValue Hi = Op.getOperand(1);
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
-
+
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
@@ -3094,7 +3094,7 @@
//
// If this is a vector of constants or undefs, get the bits. A bit in
-// UndefBits is set if the corresponding element of the vector is an
+// UndefBits is set if the corresponding element of the vector is an
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
// zero. Return true if this is not an array of constants, false if it is.
//
@@ -3102,11 +3102,11 @@
uint64_t UndefBits[2]) {
// Start with zero'd results.
VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
-
+
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
SDValue OpVal = BV->getOperand(i);
-
+
unsigned PartNo = i >= e/2; // In the upper 128 bits?
unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
@@ -3125,32 +3125,32 @@
// Nonconstant element.
return true;
}
-
+
VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
}
-
- //printf("%llx %llx %llx %llx\n",
+
+ //printf("%llx %llx %llx %llx\n",
// VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
return false;
}
// If this is a splat (repetition) of a value across the whole vector, return
// the smallest size that splats it. For example, "0x01010101010101..." is a
-// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
+// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
// SplatSize = 1 byte.
-static bool isConstantSplat(const uint64_t Bits128[2],
+static bool isConstantSplat(const uint64_t Bits128[2],
const uint64_t Undef128[2],
unsigned &SplatBits, unsigned &SplatUndef,
unsigned &SplatSize) {
-
+
// Don't let undefs prevent splats from matching. See if the top 64-bits are
// the same as the lower 64-bits, ignoring undefs.
if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
return false; // Can't be a splat if two pieces don't match.
-
+
uint64_t Bits64 = Bits128[0] | Bits128[1];
uint64_t Undef64 = Undef128[0] & Undef128[1];
-
+
// Check that the top 32-bits are the same as the lower 32-bits, ignoring
// undefs.
if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
@@ -3167,7 +3167,7 @@
SplatSize = 4;
return true;
}
-
+
uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
@@ -3179,7 +3179,7 @@
SplatSize = 2;
return true;
}
-
+
// Otherwise, we have an 8-bit splat.
SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
@@ -3198,13 +3198,13 @@
};
MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
-
+
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
if (Val == -1)
SplatSize = 1;
-
+
MVT CanonicalVT = VTys[SplatSize-1];
-
+
// Build a canonical splat for this value.
SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
SmallVector<SDValue, 8> Ops;
@@ -3256,28 +3256,28 @@
// selects to a single instruction, return Op. Otherwise, if we can codegen
// this case more efficiently than a constant pool load, lower it to the
// sequence of ops that should be used.
-SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
+SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) {
// If this is a vector of constants or undefs, get the bits. A bit in
- // UndefBits is set if the corresponding element of the vector is an
+ // UndefBits is set if the corresponding element of the vector is an
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
- // zero.
+ // zero.
uint64_t VectorBits[2];
uint64_t UndefBits[2];
DebugLoc dl = Op.getDebugLoc();
if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
return SDValue(); // Not a constant vector.
-
+
// If this is a splat (repetition) of a value across the whole vector, return
// the smallest size that splats it. For example, "0x01010101010101..." is a
- // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
+ // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
// SplatSize = 1 byte.
unsigned SplatBits, SplatUndef, SplatSize;
if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
-
+
// First, handle single instruction cases.
-
+
// All zeros?
if (SplatBits == 0) {
// Canonicalize all zero vectors to be v4i32.
@@ -3293,10 +3293,10 @@
int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
if (SextVal >= -16 && SextVal <= 15)
return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
-
-
+
+
// Two instruction sequences.
-
+
// If this value is in the range [-32,30] and is even, use:
// tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
@@ -3304,18 +3304,18 @@
Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
-
- // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
+
+ // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
// for fneg/fabs.
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
// Make -1 and vspltisw -1:
SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
-
+
// Make the VSLW intrinsic, computing 0x8000_0000.
- SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
+ SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
OnesV, DAG, dl);
-
+
// xor by OnesV to invert it.
Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
@@ -3327,16 +3327,16 @@
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
};
-
+
for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
int i = SplatCsts[idx];
-
+
// Figure out what shift amount will be used by altivec if shifted by i in
// this splat size.
unsigned TypeShiftAmt = i & (SplatBitSize-1);
-
+
// vsplti + shl self.
if (SextVal == (i << (int)TypeShiftAmt)) {
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
@@ -3347,7 +3347,7 @@
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
-
+
// vsplti + srl self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
@@ -3358,7 +3358,7 @@
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
-
+
// vsplti + sra self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
@@ -3369,7 +3369,7 @@
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
-
+
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
@@ -3398,9 +3398,9 @@
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
}
}
-
+
// Three instruction sequences.
-
+
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal >= 0 && SextVal <= 31) {
SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
@@ -3416,19 +3416,19 @@
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
}
-
+
return SDValue();
}
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
/// the specified operations to build the shuffle.
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
- SDValue RHS, SelectionDAG &DAG,
+ SDValue RHS, SelectionDAG &DAG,
DebugLoc dl) {
unsigned OpNum = (PFEntry >> 26) & 0x0F;
unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
-
+
enum {
OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
OP_VMRGHW,
@@ -3441,17 +3441,17 @@
OP_VSLDOI8,
OP_VSLDOI12
};
-
+
if (OpNum == OP_COPY) {
if (LHSID == (1*9+2)*9+3) return LHS;
assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
return RHS;
}
-
+
SDValue OpLHS, OpRHS;
OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
-
+
unsigned ShufIdxs[16];
switch (OpNum) {
default: assert(0 && "Unknown i32 permute!");
@@ -3493,8 +3493,8 @@
SDValue Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
-
- return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
+
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
OpLHS, OpRHS,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
}
@@ -3503,13 +3503,13 @@
/// is a shuffle we can handle in a single instruction, return it. Otherwise,
/// return the code it can be lowered into. Worst case, it can always be
/// lowered into a vperm.
-SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
+SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDValue PermMask = Op.getOperand(2);
-
+
// Cases that are handled by instructions that take permute immediates
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
// selected by the instruction selector.
@@ -3529,7 +3529,7 @@
return Op;
}
}
-
+
// Altivec has a variety of "shuffle immediates" that take two vector inputs
// and produce a fixed permutation. If any of these match, do not lower to
// VPERM.
@@ -3543,7 +3543,7 @@
PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
return Op;
-
+
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
// perfect shuffle table to emit an optimal matching sequence.
unsigned PFIndexes[4];
@@ -3553,14 +3553,14 @@
for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
continue; // Undef, ignore it.
-
- unsigned ByteSource =
+
+ unsigned ByteSource =
cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
if ((ByteSource & 3) != j) {
isFourElementShuffle = false;
break;
}
-
+
if (EltNo == 8) {
EltNo = ByteSource/4;
} else if (EltNo != ByteSource/4) {
@@ -3570,18 +3570,18 @@
}
PFIndexes[i] = EltNo;
}
-
- // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
+
+ // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
// perfect shuffle vector to determine if it is cost effective to do this as
// discrete instructions, or whether we should use a vperm.
if (isFourElementShuffle) {
// Compute the index in the perfect shuffle table.
- unsigned PFTableIndex =
+ unsigned PFTableIndex =
PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
-
+
unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
unsigned Cost = (PFEntry >> 30);
-
+
// Determining when to avoid vperm is tricky. Many things affect the cost
// of vperm, particularly how many times the perm mask needs to be computed.
// For example, if the perm mask can be hoisted out of a loop or is already
@@ -3590,35 +3590,35 @@
// the loop requires an extra register.
//
// As a compromise, we only emit discrete instructions if the shuffle can be
- // generated in 3 or fewer operations. When we have loop information
+ // generated in 3 or fewer operations. When we have loop information
// available, if this block is within a loop, we should avoid using vperm
// for 3-operation perms and use a constant pool load instead.
- if (Cost < 3)
+ if (Cost < 3)
return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
}
-
+
// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
// vector that will get spilled to the constant pool.
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
-
+
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
// that it is in input element units, not in bytes. Convert now.
MVT EltVT = V1.getValueType().getVectorElementType();
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
-
+
SmallVector<SDValue, 16> ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
unsigned SrcElt;
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
SrcElt = 0;
- else
+ else
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
-
+
for (unsigned j = 0; j != BytesPerElement; ++j)
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
MVT::i8));
}
-
+
SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
@@ -3649,7 +3649,7 @@
case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
-
+
// Normal Comparisons.
case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
@@ -3670,7 +3670,7 @@
/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
/// lower, do it, otherwise return null.
-SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
+SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) {
// If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison.
@@ -3679,7 +3679,7 @@
bool isDot;
if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
return SDValue(); // Don't custom lower most intrinsics.
-
+
// If this is a non-dot comparison, make the VCMP node and we are done.
if (!isDot) {
SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
@@ -3687,7 +3687,7 @@
DAG.getConstant(CompareOpc, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
}
-
+
// Create the PPCISD altivec 'dot' comparison node.
SDValue Ops[] = {
Op.getOperand(2), // LHS
@@ -3698,13 +3698,13 @@
VTs.push_back(Op.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
-
+
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
DAG.getRegister(PPC::CR6, MVT::i32),
- CompNode.getValue(1));
-
+ CompNode.getValue(1));
+
// Unpack the result based on how the target uses it.
unsigned BitNo; // Bit # of CR6.
bool InvertBit; // Invert result?
@@ -3723,14 +3723,14 @@
BitNo = 2; InvertBit = true;
break;
}
-
+
// Shift the bit into the low position.
Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
DAG.getConstant(8-(3-BitNo), MVT::i32));
// Isolate the bit.
Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
DAG.getConstant(1, MVT::i32));
-
+
// If we are supposed to, toggle the bit.
if (InvertBit)
Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
@@ -3738,7 +3738,7 @@
return Flags;
}
-SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
+SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Create a stack slot that is 16-byte aligned.
@@ -3746,7 +3746,7 @@
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
-
+
// Store the input value into Value#0 of the stack slot.
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Op.getOperand(0), FIdx, NULL, 0);
@@ -3758,49 +3758,49 @@
DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v4i32) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
-
+
SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
-
+
SDValue RHSSwap = // = vrlw RHS, 16
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
-
+
// Shrinkify inputs to v8i16.
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
-
+
// Low parts multiplied together, generating 32-bit results (we ignore the
// top parts).
SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
LHS, RHS, DAG, dl, MVT::v4i32);
-
+
SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
// Shift the high parts up 16 bits.
- HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
+ HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
Neg16, DAG, dl);
return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
} else if (Op.getValueType() == MVT::v8i16) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
-
+
SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
LHS, RHS, Zero, DAG, dl);
} else if (Op.getValueType() == MVT::v16i8) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
-
+
// Multiply the even 8-bit parts, producing 16-bit sums.
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
LHS, RHS, DAG, dl, MVT::v8i16);
EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
-
+
// Multiply the odd 8-bit parts, producing 16-bit sums.
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
LHS, RHS, DAG, dl, MVT::v8i16);
OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
-
+
// Merge the results together.
SDValue Ops[16];
for (unsigned i = 0; i != 8; ++i) {
@@ -3819,23 +3819,23 @@
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: assert(0 && "Wasn't expecting to be able to lower this!");
+ default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
- case ISD::VASTART:
+ case ISD::VASTART:
return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
-
- case ISD::VAARG:
+
+ case ISD::VAARG:
return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
case ISD::FORMAL_ARGUMENTS:
- return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
+ return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
VarArgsStackOffset, VarArgsNumGPR,
VarArgsNumFPR, PPCSubTarget);
@@ -3863,7 +3863,7 @@
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
case ISD::MUL: return LowerMUL(Op, DAG);
-
+
// Frame & Return address.
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
@@ -3882,7 +3882,7 @@
case ISD::FP_ROUND_INREG: {
assert(N->getValueType(0) == MVT::ppcf128);
assert(N->getOperand(0).getValueType() == MVT::ppcf128);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(0));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
@@ -3936,7 +3936,7 @@
// We know the low half is about to be thrown away, so just use something
// convenient.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
FPreg, FPreg));
return;
}
@@ -3999,7 +3999,7 @@
BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
BuildMI(BB, dl, TII->get(PPC::BCC))
- .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
+ .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -4010,7 +4010,7 @@
}
MachineBasicBlock *
-PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
+PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
MachineBasicBlock *BB,
bool is8bit, // operation
unsigned BinOpcode) const {
@@ -4040,7 +4040,7 @@
exitMBB->transferSuccessors(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
- const TargetRegisterClass *RC =
+ const TargetRegisterClass *RC =
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
(const TargetRegisterClass *) &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
@@ -4125,7 +4125,7 @@
BuildMI(BB, dl, TII->get(PPC::STWCX))
.addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
BuildMI(BB, dl, TII->get(PPC::BCC))
- .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
+ .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -4180,15 +4180,15 @@
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
-
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
BB = copy0MBB;
-
+
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
-
+
// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
@@ -4315,7 +4315,7 @@
BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
-
+
BB = midMBB;
BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(dest).addReg(ptrA).addReg(ptrB);
@@ -4350,7 +4350,7 @@
exitMBB->transferSuccessors(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
- const TargetRegisterClass *RC =
+ const TargetRegisterClass *RC =
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
(const TargetRegisterClass *) &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
@@ -4459,7 +4459,7 @@
BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
-
+
BB = midMBB;
BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
@@ -4507,7 +4507,7 @@
return N->getOperand(0);
}
break;
-
+
case ISD::SINT_TO_FP:
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
@@ -4521,13 +4521,13 @@
Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
-
+
Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
if (N->getValueType(0) == MVT::f32) {
- Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
+ Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
DAG.getIntPtrConstant(0));
DCI.AddToWorklist(Val.getNode());
}
@@ -4559,7 +4559,7 @@
DCI.AddToWorklist(Val.getNode());
return Val;
}
-
+
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
N->getOperand(1).getNode()->hasOneUse() &&
@@ -4595,11 +4595,11 @@
};
SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
- // If this is an i16 load, insert the truncate.
+ // If this is an i16 load, insert the truncate.
SDValue ResVal = BSLoad;
if (N->getValueType(0) == MVT::i16)
ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
-
+
// First, combine the bswap away. This makes the value produced by the
// load dead.
DCI.CombineTo(N, ResVal);
@@ -4607,11 +4607,11 @@
// Next, combine the load away, we give it a bogus result value but a real
// chain result. The result value is dead because the bswap is dead.
DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
-
+
// Return N so it doesn't get rechecked!
return SDValue(N, 0);
}
-
+
break;
case PPCISD::VCMP: {
// If a VCMPo node already exists with exactly the same operands as this
@@ -4621,10 +4621,10 @@
if (!N->getOperand(0).hasOneUse() &&
!N->getOperand(1).hasOneUse() &&
!N->getOperand(2).hasOneUse()) {
-
+
// Scan all of the users of the LHS, looking for VCMPo's that match.
SDNode *VCMPoNode = 0;
-
+
SDNode *LHSN = N->getOperand(0).getNode();
for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
UI != E; ++UI)
@@ -4635,17 +4635,17 @@
VCMPoNode = *UI;
break;
}
-
+
// If there is no VCMPo node, or if the flag value has a single use, don't
// transform this.
if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
break;
-
- // Look at the (necessarily single) use of the flag value. If it has a
+
+ // Look at the (necessarily single) use of the flag value. If it has a
// chain, this transformation is more complex. Note that multiple things
// could use the value result, which we should ignore.
SDNode *FlagUser = 0;
- for (SDNode::use_iterator UI = VCMPoNode->use_begin();
+ for (SDNode::use_iterator UI = VCMPoNode->use_begin();
FlagUser == 0; ++UI) {
assert(UI != VCMPoNode->use_end() && "Didn't find user!");
SDNode *User = *UI;
@@ -4656,7 +4656,7 @@
}
}
}
-
+
// If the user is a MFCR instruction, we know this is safe. Otherwise we
// give up for right now.
if (FlagUser->getOpcode() == PPCISD::MFCR)
@@ -4673,12 +4673,12 @@
SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
int CompareOpc;
bool isDot;
-
+
if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
assert(isDot && "Can't compare against a vector result!");
-
+
// If this is a comparison against something other than 0/1, then we know
// that the condition is never/always true.
unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
@@ -4689,9 +4689,9 @@
return DAG.getNode(ISD::BR, dl, MVT::Other,
N->getOperand(0), N->getOperand(4));
}
-
+
bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
-
+
// Create the PPCISD altivec 'dot' comparison node.
std::vector<MVT> VTs;
SDValue Ops[] = {
@@ -4702,7 +4702,7 @@
VTs.push_back(LHS.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
-
+
// Unpack the result based on how the target uses it.
PPC::Predicate CompOpc;
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
@@ -4729,7 +4729,7 @@
break;
}
}
-
+
return SDValue();
}
@@ -4739,7 +4739,7 @@
void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
- APInt &KnownZero,
+ APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth) const {
@@ -4770,7 +4770,7 @@
case Intrinsic::ppc_altivec_vcmpgtuw_p:
KnownZero = ~1U; // All bits but the low one are known to be zero.
break;
- }
+ }
}
}
}
@@ -4778,7 +4778,7 @@
/// getConstraintType - Given a constraint, return the type of
/// constraint it is for this target.
-PPCTargetLowering::ConstraintType
+PPCTargetLowering::ConstraintType
PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
@@ -4794,7 +4794,7 @@
return TargetLowering::getConstraintType(Constraint);
}
-std::pair<unsigned, const TargetRegisterClass*>
+std::pair<unsigned, const TargetRegisterClass*>
PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const {
if (Constraint.size() == 1) {
@@ -4811,13 +4811,13 @@
else if (VT == MVT::f64)
return std::make_pair(0U, PPC::F8RCRegisterClass);
break;
- case 'v':
+ case 'v':
return std::make_pair(0U, PPC::VRRCRegisterClass);
case 'y': // crrc
return std::make_pair(0U, PPC::CRRCRegisterClass);
}
}
-
+
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
@@ -4867,7 +4867,7 @@
if ((int)Value > 0 && isPowerOf2_32(Value))
Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
- case 'O': // "O" is the constant zero.
+ case 'O': // "O" is the constant zero.
if (Value == 0)
Result = DAG.getTargetConstant(Value, Op.getValueType());
break;
@@ -4879,31 +4879,31 @@
break;
}
}
-
+
if (Result.getNode()) {
Ops.push_back(Result);
return;
}
-
+
// Handle standard constraint letters.
TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
}
// isLegalAddressingMode - Return true if the addressing mode represented
// by AM is legal for this target, for a load/store of the specified type.
-bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
+bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const {
// FIXME: PPC does not allow r+i addressing modes for vectors!
-
+
// PPC allows a sign-extended 16-bit immediate field.
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
return false;
-
+
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
-
- // PPC only support r+r,
+
+ // PPC only support r+r,
switch (AM.Scale) {
case 0: // "r+i" or just "i", depending on HasBaseReg.
break;
@@ -4921,7 +4921,7 @@
// No other scales are supported.
return false;
}
-
+
return true;
}
@@ -4934,12 +4934,12 @@
}
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
- return false;
+ return false;
}
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- // Depths > 0 not supported yet!
+ // Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
@@ -4952,22 +4952,22 @@
// Make sure the function really does not optimize away the store of the RA
// to the stack.
FuncInfo->setLRStoreRequired();
- return DAG.getLoad(getPointerTy(), dl,
+ return DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), RetAddrFI, NULL, 0);
}
SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- // Depths > 0 not supported yet!
+ // Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
-
+
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
-
+
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
+ bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
&& MFI->getStackSize();
if (isPPC64)
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=64827&r1=64826&r2=64827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 17 16:15:04 2009
@@ -80,7 +80,7 @@
setUseUnderscoreSetJmp(true);
setUseUnderscoreLongJmp(true);
}
-
+
// Set up the register classes.
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
@@ -90,7 +90,7 @@
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- // We don't accept any truncstore of integer registers.
+ // We don't accept any truncstore of integer registers.
setTruncStoreAction(MVT::i64, MVT::i32, Expand);
setTruncStoreAction(MVT::i64, MVT::i16, Expand);
setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
@@ -234,7 +234,7 @@
setOperationAction(ISD::FREM , MVT::f64 , Expand);
setOperationAction(ISD::FREM , MVT::f80 , Expand);
setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
-
+
setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
@@ -448,7 +448,7 @@
if (Fast) {
setConvertAction(MVT::f32, MVT::f64, Expand);
setConvertAction(MVT::f32, MVT::f80, Expand);
- setConvertAction(MVT::f80, MVT::f32, Expand);
+ setConvertAction(MVT::f80, MVT::f32, Expand);
setConvertAction(MVT::f64, MVT::f32, Expand);
// And x87->x87 truncations also.
setConvertAction(MVT::f80, MVT::f64, Expand);
@@ -473,7 +473,7 @@
// this though and handle it in InstructionSelectPreprocess so that
// dagcombine2 can hack on these.
if (Fast) {
- setConvertAction(MVT::f80, MVT::f32, Expand);
+ setConvertAction(MVT::f80, MVT::f32, Expand);
setConvertAction(MVT::f64, MVT::f32, Expand);
setConvertAction(MVT::f80, MVT::f64, Expand);
}
@@ -512,7 +512,7 @@
TmpFlt2.changeSign();
addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
}
-
+
if (!UnsafeFPMath) {
setOperationAction(ISD::FSIN , MVT::f80 , Expand);
setOperationAction(ISD::FCOS , MVT::f80 , Expand);
@@ -761,7 +761,7 @@
setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
-
+
}
if (Subtarget->hasSSE41()) {
@@ -791,7 +791,7 @@
if (Subtarget->hasSSE42()) {
setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
}
-
+
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@@ -926,13 +926,13 @@
SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
-
+
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
-
+
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
@@ -941,7 +941,7 @@
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
SDValue Chain = Op.getOperand(0);
-
+
// Handle tail call return.
Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
if (Chain.getOpcode() == X86ISD::TAILCALL) {
@@ -952,7 +952,7 @@
(cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
- TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
+ TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
"Expecting an global address, external symbol, or register");
assert(StackAdjustment.getOpcode() == ISD::Constant &&
"Expecting a const value");
@@ -966,10 +966,10 @@
for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Operands.push_back(Chain.getOperand(i));
}
- return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
+ return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
Operands.size());
}
-
+
// Regular return.
SDValue Flag;
@@ -977,13 +977,13 @@
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
-
+
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
SDValue ValToCopy = Op.getOperand(i*2+1);
-
+
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
// the RET instruction and handled by the FP Stackifier.
if (VA.getLocReg() == X86::ST0 ||
@@ -1019,14 +1019,14 @@
Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
Flag = Chain.getValue(1);
}
-
+
RetOps[0] = Chain; // Update chain.
// Add the flag if we have it.
if (Flag.getNode())
RetOps.push_back(Flag);
-
- return DAG.getNode(X86ISD::RET_FLAG, dl,
+
+ return DAG.getNode(X86ISD::RET_FLAG, dl,
MVT::Other, &RetOps[0], RetOps.size());
}
@@ -1037,10 +1037,10 @@
/// being lowered. The returns a SDNode with the same number of values as the
/// ISD::CALL.
SDNode *X86TargetLowering::
-LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
+LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
- DebugLoc dl = TheCall->getDebugLoc();
+ DebugLoc dl = TheCall->getDebugLoc();
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
bool isVarArg = TheCall->isVarArg();
@@ -1049,14 +1049,14 @@
CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
SmallVector<SDValue, 8> ResultVals;
-
+
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
MVT CopyVT = VA.getValVT();
-
+
// If this is x86-64, and we disabled SSE, we can't return FP values
- if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
+ if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
cerr << "SSE register return with SSE disabled\n";
exit(1);
@@ -1070,7 +1070,7 @@
isScalarFPTypeInSSEReg(VA.getValVT())) {
CopyVT = MVT::f80;
}
-
+
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
CopyVT, InFlag).getValue(1);
SDValue Val = Chain.getValue(0);
@@ -1083,7 +1083,7 @@
// This truncation won't change the value.
DAG.getIntPtrConstant(1));
}
-
+
ResultVals.push_back(Val);
}
@@ -1197,9 +1197,9 @@
/// CallRequiresFnAddressInReg - Check whether the call requires the function
/// address to be loaded in a register.
-bool
+bool
X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
- return !Is64Bit && IsTailCall &&
+ return !Is64Bit && IsTailCall &&
getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Subtarget->isPICStyleGOT();
}
@@ -1208,7 +1208,7 @@
/// by "Src" to address "Dst" with size and alignment information specified by
/// the specific parameter attribute. The copy will be passed as a byval
/// function parameter.
-static SDValue
+static SDValue
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
@@ -1229,7 +1229,7 @@
bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
// FIXME: For now, all byval parameter objects are marked mutable. This can be
- // changed with more analysis.
+ // changed with more analysis.
// In case of tail call optimization mark all arguments mutable. Since they
// could be overwritten by lowering of arguments in case of a tail call.
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
@@ -1246,7 +1246,7 @@
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
DebugLoc dl = Op.getDebugLoc();
-
+
const Function* Fn = MF.getFunction();
if (Fn->hasExternalLinkage() &&
Subtarget->isTargetCygMing() &&
@@ -1255,7 +1255,7 @@
// Decorate the function name.
FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
-
+
MachineFrameInfo *MFI = MF.getFrameInfo();
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
@@ -1270,7 +1270,7 @@
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
-
+
SmallVector<SDValue, 8> ArgValues;
unsigned LastVal = ~0U;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -1280,7 +1280,7 @@
assert(VA.getValNo() != LastVal &&
"Don't support value assigned to multiple locs yet");
LastVal = VA.getValNo();
-
+
if (VA.isRegLoc()) {
MVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = NULL;
@@ -1315,7 +1315,7 @@
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
-
+
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the
// right size.
@@ -1325,10 +1325,10 @@
else if (VA.getLocInfo() == CCValAssign::ZExt)
ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
-
+
if (VA.getLocInfo() != CCValAssign::Full)
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
-
+
// Handle MMX values passed in GPRs.
if (Is64Bit && RegVT != VA.getLocVT()) {
if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
@@ -1339,7 +1339,7 @@
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
}
}
-
+
ArgValues.push_back(ArgValue);
} else {
assert(VA.isMemLoc());
@@ -1459,7 +1459,7 @@
&MemOps[0], MemOps.size());
}
}
-
+
ArgValues.push_back(Root);
// Some CCs need callee pop.
@@ -1470,7 +1470,7 @@
BytesToPopOnReturn = 0; // Callee pops nothing.
// If this is an sret function, the return should pop the hidden pointer.
if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
- BytesToPopOnReturn = 4;
+ BytesToPopOnReturn = 4;
BytesCallerReserves = StackSize;
}
@@ -1506,12 +1506,12 @@
/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
/// optimization is performed and it is required.
-SDValue
-X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
+SDValue
+X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
SDValue &OutRetAddr,
- SDValue Chain,
- bool IsTailCall,
- bool Is64Bit,
+ SDValue Chain,
+ bool IsTailCall,
+ bool Is64Bit,
int FPDiff,
DebugLoc dl) {
if (!IsTailCall || FPDiff==0) return Chain;
@@ -1527,19 +1527,19 @@
/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
/// optimization is performed and it is required (FPDiff!=0).
-static SDValue
-EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
+static SDValue
+EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
SDValue Chain, SDValue RetAddrFrIdx,
bool Is64Bit, int FPDiff, DebugLoc dl) {
// Store the return address to the appropriate stack slot.
if (!FPDiff) return Chain;
// Calculate the new stack slot for the return address.
int SlotSize = Is64Bit ? 8 : 4;
- int NewReturnAddrFI =
+ int NewReturnAddrFI =
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
- Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
+ Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
return Chain;
}
@@ -1564,7 +1564,7 @@
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
-
+
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
if (PerformTailCallOpt && CC == CallingConv::Fast)
@@ -1573,7 +1573,7 @@
int FPDiff = 0;
if (IsTailCall) {
// Lower arguments at fp - stackoffset + fpdiff.
- unsigned NumBytesCallerPushed =
+ unsigned NumBytesCallerPushed =
MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
FPDiff = NumBytesCallerPushed - NumBytes;
@@ -1601,7 +1601,7 @@
SDValue Arg = TheCall->getArg(i);
ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
bool isByVal = Flags.isByVal();
-
+
// Promote the value if needed.
switch (VA.getLocInfo()) {
default: assert(0 && "Unknown loc info!");
@@ -1616,7 +1616,7 @@
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break;
}
-
+
if (VA.isRegLoc()) {
if (Is64Bit) {
MVT RegVT = VA.getLocVT();
@@ -1648,13 +1648,13 @@
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
-
+
MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
Chain, Arg, Flags));
}
}
}
-
+
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
@@ -1666,17 +1666,17 @@
// tail call optimization the copies to registers are lowered later.
if (!IsTailCall)
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
// ELF / PIC requires GOT in the EBX register before function calls via PLT
- // GOT pointer.
+ // GOT pointer.
if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
- DAG.getNode(X86ISD::GlobalBaseReg,
- DebugLoc::getUnknownLoc(),
+ DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
getPointerTy()),
InFlag);
InFlag = Chain.getValue(1);
@@ -1713,9 +1713,9 @@
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
- assert((Subtarget->hasSSE1() || !NumXMMRegs)
+ assert((Subtarget->hasSSE1() || !NumXMMRegs)
&& "SSE registers cannot be used when SSE is disabled");
-
+
Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
InFlag = Chain.getValue(1);
@@ -1745,7 +1745,7 @@
// Copy relative to framepointer.
SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
+ StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
getPointerTy());
Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
@@ -1756,7 +1756,7 @@
MemOpChains2.push_back(
DAG.getStore(Chain, dl, Arg, FIN,
PseudoSourceValue::getFixedStack(FI), 0));
- }
+ }
}
}
@@ -1766,7 +1766,7 @@
// Copy arguments to their registers.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -1792,13 +1792,13 @@
unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
Chain = DAG.getCopyToReg(Chain, dl,
- DAG.getRegister(Opc, getPointerTy()),
+ DAG.getRegister(Opc, getPointerTy()),
Callee,InFlag);
Callee = DAG.getRegister(Opc, getPointerTy());
// Add register as live out.
DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
}
-
+
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
@@ -1807,12 +1807,12 @@
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
DAG.getIntPtrConstant(0, true), InFlag);
InFlag = Chain.getValue(1);
-
+
// Returns a chain & a flag for retval copy to use.
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Ops.clear();
}
-
+
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -1824,7 +1824,7 @@
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
-
+
// Add an implicit use GOT pointer in EBX.
if (!IsTailCall && !Is64Bit &&
getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
@@ -1839,11 +1839,11 @@
Ops.push_back(InFlag);
if (IsTailCall) {
- assert(InFlag.getNode() &&
+ assert(InFlag.getNode() &&
"Flag must be set. Depend on flag being set in LowerRET");
Chain = DAG.getNode(X86ISD::TAILCALL, dl,
TheCall->getVTList(), &Ops[0], Ops.size());
-
+
return SDValue(Chain.getNode(), Op.getResNo());
}
@@ -1861,7 +1861,7 @@
NumBytesForCalleeToPush = 4;
else
NumBytesForCalleeToPush = 0; // Callee pops nothing.
-
+
// Returns a flag for retval copy to use.
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getIntPtrConstant(NumBytes, true),
@@ -1901,7 +1901,7 @@
// arg1
// arg2
// RETADDR
-// [ new RETADDR
+// [ new RETADDR
// move area ]
// (possible EBP)
// ESI
@@ -1910,13 +1910,13 @@
/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
/// for a 16 byte align requirement.
-unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
+unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
SelectionDAG& DAG) {
MachineFunction &MF = DAG.getMachineFunction();
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo &TFI = *TM.getFrameInfo();
unsigned StackAlignment = TFI.getStackAlignment();
- uint64_t AlignMask = StackAlignment - 1;
+ uint64_t AlignMask = StackAlignment - 1;
int64_t Offset = StackSize;
uint64_t SlotSize = TD->getPointerSize();
if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
@@ -1924,7 +1924,7 @@
Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
} else {
// Mask out lower bits, add stackalignment once plus the 12 bytes.
- Offset = ((~AlignMask) & Offset) + StackAlignment +
+ Offset = ((~AlignMask) & Offset) + StackAlignment +
(StackAlignment-SlotSize);
}
return Offset;
@@ -2038,7 +2038,7 @@
case ISD::SETUGE: return X86::COND_AE;
}
}
-
+
// First determine if it is required or is profitable to flip the operands.
// If LHS is a foldable load, but RHS is not, flip the condition.
@@ -2896,7 +2896,7 @@
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF)
continue;
-
+
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Idx < NumElems) {
unsigned Opc = V1.getNode()->getOpcode();
@@ -2922,7 +2922,7 @@
static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
-
+
// Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
SDValue Vec;
@@ -2943,7 +2943,7 @@
///
static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
-
+
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
@@ -2993,13 +2993,13 @@
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i, BaseVT));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
}
/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
/// of specified width.
-static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
+static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
DebugLoc dl) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
@@ -3008,7 +3008,7 @@
MaskVec.push_back(DAG.getConstant(i, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
}
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
}
@@ -3024,7 +3024,7 @@
MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
}
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
}
@@ -3040,7 +3040,7 @@
MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
}
@@ -3113,7 +3113,7 @@
assert(NumElems == 4);
SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Cst0, Cst1, Cst0, Cst1);
}
@@ -3237,7 +3237,7 @@
SDValue ThisElt(0, 0), LastElt(0, 0);
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
if (LastIsNonZero) {
- LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
+ LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
MVT::i16, Op.getOperand(i-1));
}
if (ThisIsNonZero) {
@@ -3279,7 +3279,7 @@
V = DAG.getUNDEF(MVT::v8i16);
First = false;
}
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
MVT::v8i16, V, Op.getOperand(i),
DAG.getIntPtrConstant(i));
}
@@ -3354,7 +3354,7 @@
if (NumNonZero == 1 && NumElems <= 4) {
unsigned Idx = CountTrailingZeros_32(NonZeros);
SDValue Item = Op.getOperand(Idx);
-
+
// If this is an insertion of an i64 value on x86-32, and if the top bits of
// the value are obviously zero, truncate the value to i32 and do the
// insertion that way. Only do this if the value is non-constant or if the
@@ -3366,18 +3366,18 @@
// Handle MMX and SSE both.
MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
-
+
// Truncate the value (which may itself be a constant) to i32, and
// convert it to a vector with movd (S2V+shuffle to zero extend).
Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
-
+
// Now we have our 32-bit value zero extended in the low element of
// a vector. If Idx != 0, swizzle it into place.
if (Idx != 0) {
- SDValue Ops[] = {
+ SDValue Ops[] = {
Item, DAG.getUNDEF(Item.getValueType()),
getSwapEltZeroMask(VecElts, Idx, DAG, dl)
};
@@ -3386,7 +3386,7 @@
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
}
}
-
+
// If we have a constant or non-constant insertion into the low element of
// a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
// the rest of the elements. This will be matched as movd/movq/movss/movsd
@@ -3406,11 +3406,11 @@
isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
unsigned NumBits = VT.getSizeInBits();
return getVShift(true, VT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
VT, Op.getOperand(1)),
NumBits/2, DAG, *this, dl);
}
-
+
if (IsAllConstants) // Otherwise, it's better to do a constpool load.
return SDValue();
@@ -3421,7 +3421,7 @@
// place.
if (EVTBits == 32) {
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
-
+
// Turn it into a shuffle of zero and zero-extended scalar to vector.
Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
Subtarget->hasSSE2(), DAG);
@@ -3440,7 +3440,7 @@
// Splat is obviously ok. Let legalizer expand it to a shuffle.
if (Values.size() == 1)
return SDValue();
-
+
// A vector full of immediates; various special cases are already
// handled, so this is best done with a single constant-pool load.
if (IsAllConstants)
@@ -3647,9 +3647,9 @@
if (AnyOutOrder) {
for (unsigned i = 4; i != 8; ++i)
MaskVec.push_back(DAG.getConstant(i, MaskEVT));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], 8);
- NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
+ NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
NewV, NewV, Mask);
}
}
@@ -3682,9 +3682,9 @@
}
if (AnyOutOrder) {
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
MaskVT, &MaskVec[0], 8);
- NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
+ NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
NewV, NewV, Mask);
}
}
@@ -3894,7 +3894,7 @@
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
- DAG.getNode(ISD::BIT_CONVERT, dl,
+ DAG.getNode(ISD::BIT_CONVERT, dl,
OpVT, SrcOp)));
}
@@ -3992,7 +3992,7 @@
Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, dl,
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
MaskVT, &Mask1[0], 4));
} else {
Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
@@ -4008,7 +4008,7 @@
DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
MaskEVT);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
- DAG.getNode(ISD::BUILD_VECTOR, dl,
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
MaskVT, &Mask1[0], 4));
}
}
@@ -4105,7 +4105,7 @@
SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
*this, dl);
if (NewOp.getNode())
- return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
LowerVECTOR_SHUFFLE(NewOp, DAG));
} else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this.
@@ -4138,7 +4138,7 @@
SDValue ShVal;
bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
if (isShift && ShVal.hasOneUse()) {
- // If the shifted value has multiple uses, it may be cheaper to use
+ // If the shifted value has multiple uses, it may be cheaper to use
// v_set0 + movlhps or movhlps, etc.
MVT EVT = VT.getVectorElementType();
ShAmt *= EVT.getSizeInBits();
@@ -4177,7 +4177,7 @@
// 1,1,1,1 -> v8i16 though.
V1IsSplat = isSplatVector(V1.getNode());
V2IsSplat = isSplatVector(V2.getNode());
-
+
// Canonicalize the splat or undef, if present, to be on the RHS.
if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
@@ -4328,7 +4328,7 @@
User->getValueType(0) != MVT::i32))
return SDValue();
SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
@@ -4361,7 +4361,7 @@
if (Idx == 0)
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, dl,
+ DAG.getNode(ISD::BIT_CONVERT, dl,
MVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
@@ -4413,7 +4413,7 @@
&IdxVec[0], IdxVec.size());
SDValue Vec = Op.getOperand(0);
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
- Vec, DAG.getUNDEF(Vec.getValueType()),
+ Vec, DAG.getUNDEF(Vec.getValueType()),
Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
DAG.getIntPtrConstant(0));
@@ -4448,9 +4448,9 @@
// zero here. The DAG Combiner may combine an extract_elt index into these
// bits. For example (insert (extract, 3), 2) could be matched by putting
// the '3' into bits [7:6] of X86ISD::INSERTPS.
- // Bits [5:4] of the constant are the destination select. This is the
+ // Bits [5:4] of the constant are the destination select. This is the
// value of the incoming immediate.
- // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
+ // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
@@ -4564,7 +4564,7 @@
DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
Result);
}
-
+
// For Darwin & Mingw32, external and weak symbols are indirect, so we want to
// load the value at address GV, not the value of GV itself. This means that
// the GlobalAddress must be in the base or index register of the address, not
@@ -4718,7 +4718,7 @@
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
- DAG.getNode(X86ISD::GlobalBaseReg,
+ DAG.getNode(X86ISD::GlobalBaseReg,
DebugLoc::getUnknownLoc(),
getPointerTy()),
Result);
@@ -4747,7 +4747,7 @@
}
/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
-/// take a 2 x i32 value to shift plus a shift amount.
+/// take a 2 x i32 value to shift plus a shift amount.
SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
MVT VT = Op.getValueType();
@@ -4758,7 +4758,7 @@
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
SDValue Tmp1 = isSRA ?
- DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
+ DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
DAG.getConstant(VTBits - 1, MVT::i8)) :
DAG.getConstant(0, VT);
@@ -4797,14 +4797,14 @@
MVT SrcVT = Op.getOperand(0).getValueType();
assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
-
+
// These are really Legal; caller falls through into that case.
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
return SDValue();
- if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
+ if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
Subtarget->is64Bit())
return SDValue();
-
+
DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
MachineFunction &MF = DAG.getMachineFunction();
@@ -4911,12 +4911,12 @@
MaskVec.push_back(DAG.getConstant(4, MVT::i32));
MaskVec.push_back(DAG.getConstant(1, MVT::i32));
MaskVec.push_back(DAG.getConstant(5, MVT::i32));
- SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&MaskVec[0], MaskVec.size());
SmallVector<SDValue, 4> MaskVec2;
MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
- SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
&MaskVec2[0], MaskVec2.size());
SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
@@ -5027,7 +5027,7 @@
"Unknown FP_TO_SINT to lower!");
// These are really Legal.
- if (Op.getValueType() == MVT::i32 &&
+ if (Op.getValueType() == MVT::i32 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
if (Subtarget->is64Bit() &&
@@ -5076,7 +5076,7 @@
std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
SDValue FIST = Vals.first, StackSlot = Vals.second;
if (FIST.getNode() == 0) return SDValue();
-
+
// Load the result.
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
FIST, StackSlot, NULL, 0);
@@ -5137,7 +5137,7 @@
if (VT.isVector()) {
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(ISD::XOR, dl, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
Op.getOperand(0)),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
} else {
@@ -5223,7 +5223,7 @@
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
-
+
// Lower (X & (1 << N)) == 0 to BT(X, N).
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
// Lower ((X >>s N) & 1) != 0 to BT(X, N).
@@ -5278,7 +5278,7 @@
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
-
+
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(X86CC, MVT::i8), Cond);
@@ -5305,7 +5305,7 @@
default: break;
case ISD::SETOEQ:
case ISD::SETEQ: SSECC = 0; break;
- case ISD::SETOGT:
+ case ISD::SETOGT:
case ISD::SETGT: Swap = true; // Fallthrough
case ISD::SETLT:
case ISD::SETOLT: SSECC = 1; break;
@@ -5344,13 +5344,13 @@
// Handle all other FP comparisons here.
return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
}
-
+
// We are handling one of the integer comparisons here. Since SSE only has
// GT and EQ comparisons for integer, swapping operands and multiple
// operations may be required for some comparisons.
unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
bool Swap = false, Invert = false, FlipSigns = false;
-
+
switch (VT.getSimpleVT()) {
default: break;
case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
@@ -5358,7 +5358,7 @@
case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
}
-
+
switch (SetCCOpcode) {
default: break;
case ISD::SETNE: Invert = true;
@@ -5374,7 +5374,7 @@
}
if (Swap)
std::swap(Op0, Op1);
-
+
// Since SSE has no unsigned integer comparisons, we need to flip the sign
// bits of the inputs before performing those operations.
if (FlipSigns) {
@@ -5387,7 +5387,7 @@
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
}
-
+
SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
// If the logical-not of the result is required, perform that now.
@@ -5419,12 +5419,12 @@
SDValue Cmp = Cond.getOperand(1);
unsigned Opc = Cmp.getOpcode();
MVT VT = Op.getValueType();
-
+
bool IllegalFPCMov = false;
if (VT.isFloatingPoint() && !VT.isVector() &&
!isScalarFPTypeInSSEReg(VT)) // FPStack?
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
-
+
if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
Cond = Cmp;
addTest = false;
@@ -5433,7 +5433,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
+ Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
DAG.getConstant(0, MVT::i8));
}
@@ -5493,7 +5493,7 @@
Cond.getOpcode() == X86ISD::UMUL)
Cond = LowerXALUO(Cond, DAG);
#endif
-
+
// If condition flag is set by a X86ISD::CMP, then use it as the condition
// setting operand in place of the X86ISD::SETCC.
if (Cond.getOpcode() == X86ISD::SETCC) {
@@ -5585,7 +5585,7 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
+ Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
DAG.getConstant(0, MVT::i8));
}
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
@@ -5665,7 +5665,7 @@
V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
MVT IntPtr = getPointerTy();
const Type *IntPtrTy = TD->getIntPtrType();
- TargetLowering::ArgListTy Args;
+ TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Entry.Node = Dst;
Entry.Ty = IntPtrTy;
@@ -5673,8 +5673,8 @@
Entry.Node = Size;
Args.push_back(Entry);
std::pair<SDValue,SDValue> CallResult =
- LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
- CallingConv::C, false,
+ LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
+ CallingConv::C, false,
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
return CallResult.second;
}
@@ -5735,11 +5735,11 @@
InFlag = Chain.getValue(1);
}
- Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
X86::ECX,
Count, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
X86::EDI,
Dst, InFlag);
InFlag = Chain.getValue(1);
@@ -5757,7 +5757,7 @@
MVT CVT = Count.getValueType();
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
- Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
+ Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
X86::ECX,
Left, InFlag);
InFlag = Chain.getValue(1);
@@ -5791,7 +5791,7 @@
SDValue Size, unsigned Align,
bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
- const Value *SrcSV, uint64_t SrcSVOff) {
+ const Value *SrcSV, uint64_t SrcSVOff) {
// This requires the copy size to be a constant, preferrably
// within a subtarget-specific limit.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -5816,15 +5816,15 @@
unsigned BytesLeft = SizeVal % UBytes;
SDValue InFlag(0, 0);
- Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
X86::ECX,
Count, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
X86::EDI,
Dst, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
X86::ESI,
Src, InFlag);
InFlag = Chain.getValue(1);
@@ -5844,7 +5844,7 @@
MVT DstVT = Dst.getValueType();
MVT SrcVT = Src.getValueType();
MVT SizeVT = Size.getValueType();
- Results.push_back(DAG.getMemcpy(Chain, dl,
+ Results.push_back(DAG.getMemcpy(Chain, dl,
DAG.getNode(ISD::ADD, dl, DstVT, Dst,
DAG.getConstant(Offset, DstVT)),
DAG.getNode(ISD::ADD, dl, SrcVT, Src,
@@ -5855,7 +5855,7 @@
SrcSV, SrcSVOff + Offset));
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Results[0], Results.size());
}
@@ -5884,7 +5884,7 @@
MemOps.push_back(Store);
// Store fp_offset
- FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
FIN, DAG.getIntPtrConstant(4));
Store = DAG.getStore(Op.getOperand(0), dl,
DAG.getConstant(VarArgsFPOffset, MVT::i32),
@@ -5892,19 +5892,19 @@
MemOps.push_back(Store);
// Store ptr to overflow_arg_area
- FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
FIN, DAG.getIntPtrConstant(4));
SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
MemOps.push_back(Store);
// Store ptr to reg_save_area.
- FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
FIN, DAG.getIntPtrConstant(8));
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
MemOps.push_back(Store);
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
@@ -6142,14 +6142,14 @@
DAG.getConstant(TD->getPointerSize(),
Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
- DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ DAG.getNode(ISD::ADD, dl, getPointerTy(),
FrameAddr, Offset),
NULL, 0);
}
// Just load the return address.
SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
- return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
+ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
RetAddrFI, NULL, 0);
}
@@ -6227,31 +6227,31 @@
OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(2, MVT::i64));
OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
// Load the 'nest' parameter value into R10.
// R10 is specified in X86CallingConv.td
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(10, MVT::i64));
OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 10);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(12, MVT::i64));
OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
// Jump to the nested function.
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(20, MVT::i64));
OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 20);
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(22, MVT::i64));
OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
TrmpAddr, 22);
@@ -6306,27 +6306,27 @@
SDValue OutChains[4];
SDValue Addr, Disp;
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(10, MVT::i32));
Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
- OutChains[0] = DAG.getStore(Root, dl,
+ OutChains[0] = DAG.getStore(Root, dl,
DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Trmp, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(1, MVT::i32));
OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(5, MVT::i32));
OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
TrmpAddr, 5, false, 1);
- Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(6, MVT::i32));
OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
@@ -6463,7 +6463,7 @@
MVT VT = Op.getValueType();
assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
DebugLoc dl = Op.getDebugLoc();
-
+
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
// ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
// ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
@@ -6476,7 +6476,7 @@
SDValue A = Op.getOperand(0);
SDValue B = Op.getOperand(1);
-
+
SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
A, DAG.getConstant(32, MVT::i32));
@@ -6567,7 +6567,7 @@
case MVT::i8: Reg = X86::AL; size = 1; break;
case MVT::i16: Reg = X86::AX; size = 2; break;
case MVT::i32: Reg = X86::EAX; size = 4; break;
- case MVT::i64:
+ case MVT::i64:
assert(Subtarget->is64Bit() && "Node not type legal!");
Reg = X86::RAX; size = 8;
break;
@@ -6581,7 +6581,7 @@
cpIn.getValue(1) };
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
- SDValue cpOut =
+ SDValue cpOut =
DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
return cpOut;
}
@@ -6725,7 +6725,7 @@
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = N->getOperand(0);
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
- SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
+ SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
rd.getValue(1));
SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
eax.getValue(2));
@@ -6871,14 +6871,14 @@
// isLegalAddressingMode - Return true if the addressing mode represented
// by AM is legal for this target, for a load/store of the specified type.
-bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
+bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const {
// X86 supports extremely general addressing modes.
-
+
// X86 allows a sign-extended 32-bit immediate field as a displacement.
if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
return false;
-
+
if (AM.BaseGV) {
// We can only fold this if we don't need an extra load.
if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
@@ -6897,7 +6897,7 @@
return false;
}
}
-
+
switch (AM.Scale) {
case 0:
case 1:
@@ -6917,7 +6917,7 @@
default: // Other stuff never works.
return false;
}
-
+
return true;
}
@@ -6971,7 +6971,7 @@
if (NumElts == 4) {
return (isMOVLMask(&BVOps[0], 4) ||
isCommutedMOVL(&BVOps[0], 4, true) ||
- isSHUFPMask(&BVOps[0], 4) ||
+ isSHUFPMask(&BVOps[0], 4) ||
isCommutedSHUFP(&BVOps[0], 4));
}
return false;
@@ -7007,7 +7007,7 @@
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
MachineFunction::iterator MBBIter = MBB;
++MBBIter;
-
+
/// First build the CFG
MachineFunction *F = MBB->getParent();
MachineBasicBlock *thisMBB = MBB;
@@ -7015,17 +7015,17 @@
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
-
+
// Move all successors to thisMBB to nextMBB
nextMBB->transferSuccessors(thisMBB);
-
+
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
-
+
// newMBB jumps to itself and fall through to nextMBB
newMBB->addSuccessor(nextMBB);
newMBB->addSuccessor(newMBB);
-
+
// Insert instructions into newMBB based on incoming instruction
assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
DebugLoc dl = bInstr->getDebugLoc();
@@ -7038,7 +7038,7 @@
// x86 address has 4 operands: base, index, scale, and displacement
int lastAddrIndx = 3; // [0,3]
int valArgIndx = 4;
-
+
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
for (int i=0; i <= lastAddrIndx; ++i)
@@ -7048,7 +7048,7 @@
if (invSrc) {
MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
}
- else
+ else
tt = t1;
unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
@@ -7064,7 +7064,7 @@
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
MIB.addReg(t1);
-
+
MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
@@ -7074,7 +7074,7 @@
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
MIB.addReg(EAXreg);
-
+
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
@@ -7114,7 +7114,7 @@
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
MachineFunction::iterator MBBIter = MBB;
++MBBIter;
-
+
/// First build the CFG
MachineFunction *F = MBB->getParent();
MachineBasicBlock *thisMBB = MBB;
@@ -7122,17 +7122,17 @@
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
-
+
// Move all successors to thisMBB to nextMBB
nextMBB->transferSuccessors(thisMBB);
-
+
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
-
+
// newMBB jumps to itself and fall through to nextMBB
newMBB->addSuccessor(nextMBB);
newMBB->addSuccessor(newMBB);
-
+
DebugLoc dl = bInstr->getDebugLoc();
// Insert instructions into newMBB based on incoming instruction
// There are 8 "real" operands plus 9 implicit def/uses, ignored here.
@@ -7145,7 +7145,7 @@
// x86 address has 4 operands: base, index, scale, and displacement
int lastAddrIndx = 3; // [0,3]
-
+
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
for (int i=0; i <= lastAddrIndx; ++i)
@@ -7172,7 +7172,7 @@
unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
- if (invSrc) {
+ if (invSrc) {
MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
} else {
@@ -7210,7 +7210,7 @@
MIB.addReg(t5);
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
MIB.addReg(t6);
-
+
MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
@@ -7222,7 +7222,7 @@
MIB.addReg(X86::EAX);
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
MIB.addReg(X86::EDX);
-
+
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
@@ -7239,7 +7239,7 @@
// thisMBB:
// newMBB:
// ld t1 = [min/max.addr]
- // mov t2 = [min/max.val]
+ // mov t2 = [min/max.val]
// cmp t1, t2
// cmov[cond] t2 = t1
// mov EAX = t1
@@ -7251,7 +7251,7 @@
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
MachineFunction::iterator MBBIter = MBB;
++MBBIter;
-
+
/// First build the CFG
MachineFunction *F = MBB->getParent();
MachineBasicBlock *thisMBB = MBB;
@@ -7259,17 +7259,17 @@
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
-
+
// Move all successors to thisMBB to nextMBB
nextMBB->transferSuccessors(thisMBB);
-
+
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
-
+
// newMBB jumps to newMBB and fall through to nextMBB
newMBB->addSuccessor(nextMBB);
newMBB->addSuccessor(newMBB);
-
+
DebugLoc dl = mInstr->getDebugLoc();
// Insert instructions into newMBB based on incoming instruction
assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
@@ -7278,11 +7278,11 @@
int numArgs = mInstr->getNumOperands() - 1;
for (int i=0; i < numArgs; ++i)
argOpers[i] = &mInstr->getOperand(i+1);
-
+
// x86 address has 4 operands: base, index, scale, and displacement
int lastAddrIndx = 3; // [0,3]
int valArgIndx = 4;
-
+
unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
for (int i=0; i <= lastAddrIndx; ++i)
@@ -7292,11 +7292,11 @@
assert((argOpers[valArgIndx]->isReg() ||
argOpers[valArgIndx]->isImm()) &&
"invalid operand");
-
- unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
+
+ unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
if (argOpers[valArgIndx]->isReg())
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
- else
+ else
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
(*MIB).addOperand(*argOpers[valArgIndx]);
@@ -7320,10 +7320,10 @@
MIB.addReg(t3);
assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
-
+
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
MIB.addReg(X86::EAX);
-
+
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
@@ -7414,7 +7414,7 @@
// Load the old value of the high byte of the control word...
unsigned OldCW =
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
- addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
CWFrameIdx);
// Set the high part to be round to zero...
@@ -7475,19 +7475,19 @@
}
case X86::ATOMAND32:
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
- X86::AND32ri, X86::MOV32rm,
+ X86::AND32ri, X86::MOV32rm,
X86::LCMPXCHG32, X86::MOV32rr,
X86::NOT32r, X86::EAX,
X86::GR32RegisterClass);
case X86::ATOMOR32:
- return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
- X86::OR32ri, X86::MOV32rm,
+ return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
+ X86::OR32ri, X86::MOV32rm,
X86::LCMPXCHG32, X86::MOV32rr,
X86::NOT32r, X86::EAX,
X86::GR32RegisterClass);
case X86::ATOMXOR32:
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
- X86::XOR32ri, X86::MOV32rm,
+ X86::XOR32ri, X86::MOV32rm,
X86::LCMPXCHG32, X86::MOV32rr,
X86::NOT32r, X86::EAX,
X86::GR32RegisterClass);
@@ -7513,7 +7513,7 @@
X86::NOT16r, X86::AX,
X86::GR16RegisterClass);
case X86::ATOMOR16:
- return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
+ return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
X86::OR16ri, X86::MOV16rm,
X86::LCMPXCHG16, X86::MOV16rr,
X86::NOT16r, X86::AX,
@@ -7546,7 +7546,7 @@
X86::NOT8r, X86::AL,
X86::GR8RegisterClass);
case X86::ATOMOR8:
- return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
+ return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
X86::OR8ri, X86::MOV8rm,
X86::LCMPXCHG8, X86::MOV8rr,
X86::NOT8r, X86::AL,
@@ -7567,19 +7567,19 @@
// This group is for 64-bit host.
case X86::ATOMAND64:
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
- X86::AND64ri32, X86::MOV64rm,
+ X86::AND64ri32, X86::MOV64rm,
X86::LCMPXCHG64, X86::MOV64rr,
X86::NOT64r, X86::RAX,
X86::GR64RegisterClass);
case X86::ATOMOR64:
- return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
- X86::OR64ri32, X86::MOV64rm,
+ return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
+ X86::OR64ri32, X86::MOV64rm,
X86::LCMPXCHG64, X86::MOV64rr,
X86::NOT64r, X86::RAX,
X86::GR64RegisterClass);
case X86::ATOMXOR64:
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
- X86::XOR64ri32, X86::MOV64rm,
+ X86::XOR64ri32, X86::MOV64rm,
X86::LCMPXCHG64, X86::MOV64rr,
X86::NOT64r, X86::RAX,
X86::GR64RegisterClass);
@@ -7600,37 +7600,37 @@
// This group does 64-bit operations on a 32-bit host.
case X86::ATOMAND6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::AND32rr, X86::AND32rr,
X86::AND32ri, X86::AND32ri,
false);
case X86::ATOMOR6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::OR32rr, X86::OR32rr,
X86::OR32ri, X86::OR32ri,
false);
case X86::ATOMXOR6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::XOR32rr, X86::XOR32rr,
X86::XOR32ri, X86::XOR32ri,
false);
case X86::ATOMNAND6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::AND32rr, X86::AND32rr,
X86::AND32ri, X86::AND32ri,
true);
case X86::ATOMADD6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::ADD32rr, X86::ADC32rr,
X86::ADD32ri, X86::ADC32ri,
false);
case X86::ATOMSUB6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::SUB32rr, X86::SBB32rr,
X86::SUB32ri, X86::SBB32ri,
false);
case X86::ATOMSWAP6432:
- return EmitAtomicBit6432WithCustomInserter(MI, BB,
+ return EmitAtomicBit6432WithCustomInserter(MI, BB,
X86::MOV32rr, X86::MOV32rr,
X86::MOV32ri, X86::MOV32ri,
false);
@@ -7751,7 +7751,7 @@
LoadSDNode *LD = cast<LoadSDNode>(Base);
if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
- LD->getSrcValue(), LD->getSrcValueOffset(),
+ LD->getSrcValue(), LD->getSrcValueOffset(),
LD->isVolatile());
return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
@@ -7794,7 +7794,7 @@
// Transform it into VZEXT_LOAD addr.
LoadSDNode *LD = cast<LoadSDNode>(Base);
-
+
// Load must not be an extload.
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
return SDValue();
@@ -7810,7 +7810,7 @@
TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
DCI.CommitTargetLoweringOpt(TLO);
return ResNode;
-}
+}
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
@@ -7895,11 +7895,11 @@
// so we have no knowledge of the shift amount.
if (!Subtarget->hasSSE2())
return SDValue();
-
+
MVT VT = N->getValueType(0);
if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
return SDValue();
-
+
SDValue ShAmtOp = N->getOperand(1);
MVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
@@ -8017,14 +8017,14 @@
DebugLoc dl = N->getDebugLoc();
// If we are a 64-bit capable x86, lower to a single movq load/store pair.
if (Subtarget->is64Bit()) {
- SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
- Ld->getBasePtr(), Ld->getSrcValue(),
+ SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
+ Ld->getBasePtr(), Ld->getSrcValue(),
Ld->getSrcValueOffset(), Ld->isVolatile(),
Ld->getAlignment());
SDValue NewChain = NewLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(NewChain);
- NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
Ops.size());
}
return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(),
@@ -8042,14 +8042,14 @@
Ld->isVolatile(), Ld->getAlignment());
SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
- Ld->isVolatile(),
+ Ld->isVolatile(),
MinAlign(Ld->getAlignment(), 4));
SDValue NewChain = LoLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(LoLd);
Ops.push_back(HiLd);
- NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
Ops.size());
}
@@ -8063,7 +8063,7 @@
SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr,
St->getSrcValue(),
St->getSrcValueOffset() + 4,
- St->isVolatile(),
+ St->isVolatile(),
MinAlign(St->getAlignment(), 4));
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt);
}
@@ -8184,7 +8184,7 @@
if (Subtarget->hasSSE1())
return "x";
}
-
+
return TargetLowering::LowerXConstraint(ConstraintVT);
}
@@ -8196,7 +8196,7 @@
std::vector<SDValue>&Ops,
SelectionDAG &DAG) const {
SDValue Result(0, 0);
-
+
switch (Constraint) {
default: break;
case 'I':
@@ -8262,7 +8262,7 @@
// an optional displacement) to be used with 'i'.
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
int64_t Offset = 0;
-
+
// Match either (GA) or (GA+C)
if (GA) {
Offset = GA->getOffset();
@@ -8280,9 +8280,9 @@
C = 0, GA = 0;
}
}
-
+
if (GA) {
- if (hasMemory)
+ if (hasMemory)
Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
Offset, DAG);
else
@@ -8296,7 +8296,7 @@
return;
}
}
-
+
if (Result.getNode()) {
Ops.push_back(Result);
return;
@@ -8346,7 +8346,7 @@
if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16RegisterClass);
if (VT == MVT::i32 || !Subtarget->is64Bit())
- return std::make_pair(0U, X86::GR32RegisterClass);
+ return std::make_pair(0U, X86::GR32RegisterClass);
return std::make_pair(0U, X86::GR64RegisterClass);
case 'f': // FP Stack registers.
// If SSE is enabled for this VT, use f80 to ensure the isel moves the
@@ -8386,7 +8386,7 @@
break;
}
}
-
+
// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.
std::pair<unsigned, const TargetRegisterClass*> Res;
@@ -8498,24 +8498,24 @@
assert(VT.isVector());
if (isTypeLegal(VT))
return VT;
-
+
// TODO: In computeRegisterProperty, we can compute the list of legal vector
// type based on element type. This would speed up our search (though
// it may not be worth it since the size of the list is relatively
// small).
MVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
-
+
// On X86, it make sense to widen any vector wider than 1
if (NElts <= 1)
return MVT::Other;
-
- for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
+
+ for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
MVT SVT = (MVT::SimpleValueType)nVT;
-
- if (isTypeLegal(SVT) &&
- SVT.getVectorElementType() == EltVT &&
+
+ if (isTypeLegal(SVT) &&
+ SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts)
return SVT;
}
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