[llvm-commits] [llvm] r64435 - in /llvm/trunk/lib/Target/Sparc: DelaySlotFiller.cpp FPMover.cpp SparcISelLowering.cpp SparcInstrInfo.cpp SparcRegisterInfo.cpp
Dale Johannesen
dalej at apple.com
Thu Feb 12 18:31:35 PST 2009
Author: johannes
Date: Thu Feb 12 20:31:35 2009
New Revision: 64435
URL: http://llvm.org/viewvc/llvm-project?rev=64435&view=rev
Log:
Remove non-DebugLoc versions of buildMI from Sparc.
Modified:
llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/trunk/lib/Target/Sparc/FPMover.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=64435&r1=64434&r2=64435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Thu Feb 12 20:31:35 2009
@@ -68,7 +68,7 @@
if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI(MBB, J, TII->get(SP::NOP));
+ BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP));
++FilledSlots;
Changed = true;
}
Modified: llvm/trunk/lib/Target/Sparc/FPMover.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/FPMover.cpp?rev=64435&r1=64434&r2=64435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/FPMover.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/FPMover.cpp Thu Feb 12 20:31:35 2009
@@ -84,6 +84,7 @@
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++;
+ DebugLoc dl = MI->getDebugLoc();
if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
MI->getOpcode() == SP::FpNEGD) {
Changed = true;
@@ -114,7 +115,7 @@
DOUT << "FPMover: the modified instr is: " << *MI;
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
- MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
+ MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
.addReg(OddSrcReg);
DOUT << "FPMover: the inserted instr is: " << *MI;
}
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=64435&r1=64434&r2=64435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Feb 12 20:31:35 2009
@@ -926,6 +926,7 @@
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned BROpcode;
unsigned CC;
+ DebugLoc dl = MI->getDebugLoc();
// Figure out the conditional branch opcode to use for this select_cc.
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SELECT_CC!");
@@ -960,7 +961,7 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
+ BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Update machine-CFG edges by transferring all successors of the current
@@ -982,7 +983,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=64435&r1=64434&r2=64435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Thu Feb 12 20:31:35 2009
@@ -107,9 +107,11 @@
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{
+ // FIXME this should probably take a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
return 1;
}
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=64435&r1=64434&r2=64435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Feb 12 20:31:35 2009
@@ -66,11 +66,12 @@
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
MachineInstr &MI = *I;
+ DebugLoc dl = MI.getDebugLoc();
int Size = MI.getOperand(0).getImm();
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
- BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
+ BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I);
}
@@ -80,6 +81,7 @@
unsigned i = 0;
MachineInstr &MI = *II;
+ DebugLoc dl = MI.getDebugLoc();
while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -102,9 +104,9 @@
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
unsigned OffHi = (unsigned)Offset >> 10U;
- BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
.addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.getOperand(i).ChangeToRegister(SP::G1, false);
@@ -118,6 +120,7 @@
void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Get the number of bytes to allocate from the FrameInfo
int NumBytes = (int) MFI->getStackSize();
@@ -136,18 +139,18 @@
NumBytes = -NumBytes;
if (NumBytes >= -4096) {
- BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
+ BuildMI(MBB, MBB.begin(), dl, TII.get(SP::SAVEri),
SP::O6).addReg(SP::O6).addImm(NumBytes);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is
// available here.
unsigned OffHi = (unsigned)NumBytes >> 10U;
- BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::ORri), SP::G1)
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
- BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::SAVErr), SP::O6)
.addReg(SP::O6).addReg(SP::G1);
}
}
@@ -155,9 +158,10 @@
void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert(MBBI->getOpcode() == SP::RETL &&
"Can only put epilog before 'retl' instruction!");
- BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
+ BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
.addReg(SP::G0);
}
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