[llvm-commits] [llvm] r64012 - in /llvm/branches/Apple/Dib: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/ARM/ test/CodeGen/X86/
Bill Wendling
isanbard at gmail.com
Sat Feb 7 01:44:49 PST 2009
Author: void
Date: Sat Feb 7 03:44:48 2009
New Revision: 64012
URL: http://llvm.org/viewvc/llvm-project?rev=64012&view=rev
Log:
Pull these revisions into dib:
63936 63938 63940 63994 63999
Modified:
llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h
llvm/branches/Apple/Dib/include/llvm/Target/TargetRegisterInfo.h
llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Dib/lib/CodeGen/MachineSink.cpp
llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp
llvm/branches/Apple/Dib/lib/CodeGen/PreAllocSplitting.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h
llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.h
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h
llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.h
llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll
llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll
Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/Target/TargetInstrInfo.h Sat Feb 7 03:44:48 2009
@@ -427,21 +427,12 @@
return false;
}
- /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
- /// live interval splitting pass should ignore barriers of the specified
- /// register class.
- virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
+ /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
+ /// instruction that defines the specified register class.
+ virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
return true;
}
- /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
- /// values.
- virtual const TargetRegisterClass *getPointerRegClass() const {
- assert(0 && "Target didn't implement getPointerRegClass!");
- abort();
- return 0; // Must return a value in order to compile with VS 2005
- }
-
/// GetInstSize - Returns the size of the specified Instruction.
///
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetRegisterInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/Target/TargetRegisterInfo.h Sat Feb 7 03:44:48 2009
@@ -421,11 +421,12 @@
return i ? RegClassBegin[i - 1] : NULL;
}
- //===--------------------------------------------------------------------===//
- // Interfaces used by the register allocator and stack frame
- // manipulation passes to move data around between registers,
- // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
- //
+ /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
+ /// values.
+ virtual const TargetRegisterClass *getPointerRegClass() const {
+ assert(0 && "Target didn't implement getPointerRegClass!");
+ return 0; // Must return a value in order to compile with VS 2005
+ }
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns NULL if it is possible to copy
@@ -478,7 +479,6 @@
int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
-
/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
/// code insertion to eliminate call frame setup and destroy pseudo
/// instructions (but only if the Target is using them). It is responsible
Modified: llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp Sat Feb 7 03:44:48 2009
@@ -38,11 +38,6 @@
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
-// Hidden options to help debugging
-static cl::opt<bool>
-EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
- cl::desc("Perform sinking on machine code"));
-
// When this works it will be on by default.
static cl::opt<bool>
DisablePostRAScheduler("disable-post-RA-scheduler",
@@ -183,11 +178,10 @@
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- if (!Fast)
+ if (!Fast) {
PM.add(createMachineLICMPass());
-
- if (EnableSinking)
PM.add(createMachineSinkingPass());
+ }
// Run pre-ra passes.
if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
Modified: llvm/branches/Apple/Dib/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/MachineSink.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/MachineSink.cpp Sat Feb 7 03:44:48 2009
@@ -167,6 +167,10 @@
} else {
// Virtual register uses are always safe to sink.
if (MO.isUse()) continue;
+
+ // If it's not safe to move defs of the register class, then abort.
+ if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg)))
+ return false;
// FIXME: This picks a successor to sink into based on having one
// successor that dominates all the uses. However, there are cases where
Modified: llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp Sat Feb 7 03:44:48 2009
@@ -235,12 +235,11 @@
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
- const TargetInstrInfo *TII, const TargetInstrDesc &II,
- unsigned Op) {
+ const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands())
return NULL;
if (II.OpInfo[Op].isLookupPtrRegClass())
- return TII->getPointerRegClass();
+ return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
@@ -488,7 +487,7 @@
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
const TargetRegisterClass *NewRC =
- getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+ getInstrOperandRegClass(TRI, MI->getDesc(), i);
// If this instruction has a use of AntiDepReg, breaking it
// is invalid.
@@ -623,7 +622,7 @@
if (!MO.isUse()) continue;
const TargetRegisterClass *NewRC =
- getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+ getInstrOperandRegClass(TRI, MI->getDesc(), i);
// For now, only allow the register to be changed if its register
// class is consistent across all uses.
Modified: llvm/branches/Apple/Dib/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/PreAllocSplitting.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/PreAllocSplitting.cpp Sat Feb 7 03:44:48 2009
@@ -1078,7 +1078,10 @@
// by the current barrier.
SmallVector<LiveInterval*, 8> Intervals;
for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
- if (TII->IgnoreRegisterClassBarriers(*RC))
+ // FIXME: If it's not safe to move any instruction that defines the barrier
+ // register class, then it means there are some special dependencies which
+ // codegen is not modelling. Ignore these barriers for now.
+ if (!TII->isSafeToMoveRegClassDefs(*RC))
continue;
std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Sat Feb 7 03:44:48 2009
@@ -32,14 +32,13 @@
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
- const TargetInstrInfo *TII, const TargetInstrDesc &II,
- unsigned Op) {
+ const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands()) {
assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
if (II.OpInfo[Op].isLookupPtrRegClass())
- return TII->getPointerRegClass();
+ return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
@@ -91,7 +90,7 @@
if (User->isMachineOpcode()) {
const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
const TargetRegisterClass *RC =
- getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
+ getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
if (!UseRC)
UseRC = RC;
else if (RC)
@@ -190,7 +189,7 @@
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
assert(RC && "Isn't a register operand!");
VRBase = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -258,8 +257,7 @@
// There may be no register class for this operand if it is a variadic
// argument (RC will be NULL in this case). In this case, we just assume
// the regclass is ok.
- const TargetRegisterClass *RC =
- getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
+ const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
assert((RC || II->isVariadic()) && "Expected reg class info!");
const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
if (RC && VRC != RC) {
@@ -327,7 +325,7 @@
// an FP vreg on x86.
assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II && !II->isVariadic()) {
- assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
+ assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
"Don't have operand info for this instruction!");
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp Sat Feb 7 03:44:48 2009
@@ -43,9 +43,6 @@
RI(*this, STI) {
}
-const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
- return &ARM::GPRRegClass;
-}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.h Sat Feb 7 03:44:48 2009
@@ -151,10 +151,6 @@
///
virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
- /// getPointerRegClass - Return the register class to use to hold pointers.
- /// This is used for addressing modes.
- virtual const TargetRegisterClass *getPointerRegClass() const;
-
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp Sat Feb 7 03:44:48 2009
@@ -191,6 +191,10 @@
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
+const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
+ return &ARM::GPRRegClass;
+}
+
/// isLowRegister - Returns true if the register is low register r0-r7.
///
bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h Sat Feb 7 03:44:48 2009
@@ -48,6 +48,10 @@
/// if the register is a single precision VFP register.
static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
+ /// getPointerRegClass - Return the register class to use to hold pointers.
+ /// This is used for addressing modes.
+ const TargetRegisterClass *getPointerRegClass() const;
+
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp Sat Feb 7 03:44:48 2009
@@ -53,14 +53,6 @@
RI(*TM.getSubtargetImpl(), *this)
{ /* NOP */ }
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *
-SPUInstrInfo::getPointerRegClass() const
-{
- return &SPU::R32CRegClass;
-}
-
bool
SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.h Sat Feb 7 03:44:48 2009
@@ -45,10 +45,6 @@
///
virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
- /// getPointerRegClass - Return the register class to use to hold pointers.
- /// This is used for addressing modes.
- virtual const TargetRegisterClass *getPointerRegClass() const;
-
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp Sat Feb 7 03:44:48 2009
@@ -216,6 +216,13 @@
return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
}
+/// getPointerRegClass - Return the register class to use to hold pointers.
+/// This is used for addressing modes.
+const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
+{
+ return &SPU::R32CRegClass;
+}
+
const unsigned *
SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
{
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.h Sat Feb 7 03:44:48 2009
@@ -41,6 +41,10 @@
*/
static unsigned getRegisterNumbering(unsigned RegEnum);
+ /// getPointerRegClass - Return the register class to use to hold pointers.
+ /// This is used for addressing modes.
+ virtual const TargetRegisterClass *getPointerRegClass() const;
+
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp Sat Feb 7 03:44:48 2009
@@ -30,16 +30,6 @@
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
RI(*TM.getSubtargetImpl(), *this) {}
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
- if (TM.getSubtargetImpl()->isPPC64())
- return &PPC::G8RCRegClass;
- else
- return &PPC::GPRCRegClass;
-}
-
-
bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg,
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h Sat Feb 7 03:44:48 2009
@@ -82,10 +82,6 @@
///
virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
- /// getPointerRegClass - Return the register class to use to hold pointers.
- /// This is used for addressing modes.
- virtual const TargetRegisterClass *getPointerRegClass() const;
-
/// Return true if the instruction is a register to register move and return
/// the source and dest operands and their sub-register indices by reference.
virtual bool isMoveInstr(const MachineInstr &MI,
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Feb 7 03:44:48 2009
@@ -137,6 +137,15 @@
ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
}
+/// getPointerRegClass - Return the register class to use to hold pointers.
+/// This is used for addressing modes.
+const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
+ if (Subtarget.isPPC64())
+ return &PPC::G8RCRegClass;
+ else
+ return &PPC::GPRCRegClass;
+}
+
const unsigned*
PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
// 32-bit Darwin calling convention.
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.h Sat Feb 7 03:44:48 2009
@@ -35,6 +35,10 @@
/// PPC::F14, return the number that it corresponds to (e.g. 14).
static unsigned getRegisterNumbering(unsigned RegEnum);
+ /// getPointerRegClass - Return the register class to use to hold pointers.
+ /// This is used for addressing modes.
+ virtual const TargetRegisterClass *getPointerRegClass() const;
+
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp Sat Feb 7 03:44:48 2009
@@ -2270,7 +2270,7 @@
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
- ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+ ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
SmallVector<MachineOperand,4> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
@@ -2345,7 +2345,7 @@
if (UnfoldStore) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
- ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+ ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
}
@@ -2369,7 +2369,7 @@
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
- ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+ ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
std::vector<SDValue> AfterOps;
@@ -2405,7 +2405,7 @@
if (TID.getNumDefs() > 0) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
DstRC = DstTOI.isLookupPtrRegClass()
- ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+ ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
@@ -2481,19 +2481,11 @@
}
bool X86InstrInfo::
-IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
- // FIXME: Ignore bariers of x87 stack registers for now. We can't
+isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
+ // FIXME: Return false for x87 stack register classes for now. We can't
// allow any loads of these registers before FpGet_ST0_80.
- return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
- RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
-}
-
-const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
- const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
- if (Subtarget->is64Bit())
- return &X86::GR64RegClass;
- else
- return &X86::GR32RegClass;
+ return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
+ RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
}
unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.h Sat Feb 7 03:44:48 2009
@@ -406,12 +406,9 @@
virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
- /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
- /// live interval splitting pass should ignore barriers of the specified
- /// register class.
- bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
-
- const TargetRegisterClass *getPointerRegClass() const;
+ /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
+ /// instruction that defines the specified register class.
+ bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp Sat Feb 7 03:44:48 2009
@@ -151,6 +151,14 @@
}
}
+const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
+ const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+ if (Subtarget->is64Bit())
+ return &X86::GR64RegClass;
+ else
+ return &X86::GR32RegClass;
+}
+
const TargetRegisterClass *
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
if (RC == &X86::CCRRegClass) {
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.h?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.h Sat Feb 7 03:44:48 2009
@@ -93,6 +93,10 @@
/// Code Generation virtual methods...
///
+ /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
+ /// values.
+ const TargetRegisterClass *getPointerRegClass() const;
+
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns NULL if it is possible to copy
/// between a two registers of the specified class.
Modified: llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/ARM/lsr-code-insertion.ll Sat Feb 7 03:44:48 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -stats |& grep {39.*Number of machine instrs printed}
+; RUN: llvm-as < %s | llc -stats |& grep {40.*Number of machine instrs printed}
; RUN: llvm-as < %s | llc -stats |& grep {.*Number of re-materialization}
; This test really wants to check that the resultant "cond_true" block only
; has a single store in it, and that cond_true55 only has code to materialize
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll?rev=64012&r1=64011&r2=64012&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/2006-05-11-InstrSched.ll Sat Feb 7 03:44:48 2009
@@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\
-; RUN: grep {asm-printer} | grep 32
+; RUN: grep {asm-printer} | grep 31
target datalayout = "e-p:32:32"
define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind {
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