[llvm-commits] [llvm] r63908 - in /llvm/branches/Apple/Dib: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/smul-with-overflow-3.ll

[Bill Wendling]

Author: void
Date: Thu Feb  5 20:06:57 2009
New Revision: 63908

URL: http://llvm.org/viewvc/llvm-project?rev=63908&view=rev
Log:
Pull r63505, r63506, and r63509 into Dib:

Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the
condition. It's normally transformed by the dag combiner, unless the condition
is set by a arithmetic op with overflow.

Modified:
    llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/Apple/Dib/test/CodeGen/X86/smul-with-overflow-3.ll

Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=63908&r1=63907&r2=63908&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Thu Feb  5 20:06:57 2009
@@ -5380,6 +5380,17 @@
   return false;
 }
 
+static bool isXor1OfSetCC(SDValue Op) {
+  if (Op.getOpcode() != ISD::XOR)
+    return false;
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  if (N1C && N1C->getAPIntValue() == 1) {
+    return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
+      Op.getOperand(0).hasOneUse();
+  }
+  return false;
+}
+
 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
   bool addTest = true;
   SDValue Chain = Op.getOperand(0);
@@ -5420,6 +5431,16 @@
         addTest = false;
         break;
       }
+    } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
+      // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
+      // It should be transformed during dag combiner except when the condition
+      // is set by a arithmetics with overflow node.
+      X86::CondCode CCode =
+        (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
+      CCode = X86::GetOppositeBranchCondition(CCode);
+      CC = DAG.getConstant(CCode, MVT::i8);
+      Cond = Cond.getOperand(0).getOperand(1);
+      addTest = false;
     }
   } else {
     unsigned CondOpc;

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/smul-with-overflow-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/smul-with-overflow-3.ll?rev=63908&r1=63907&r2=63908&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/smul-with-overflow-3.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/smul-with-overflow-3.ll Thu Feb  5 20:06:57 2009
@@ -21,3 +21,26 @@
 
 declare i32 @printf(i8*, ...) nounwind
 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
+; RUN: llvm-as < %s | llc -march=x86 | grep {jno} | count 1
+
+ at ok = internal constant [4 x i8] c"%d\0A\00"
+ at no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i32 %v1, i32 %v2) nounwind {
+entry:
+  %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+  %sum = extractvalue {i32, i1} %t, 0
+  %obit = extractvalue {i32, i1} %t, 1
+  br i1 %obit, label %overflow, label %normal
+
+overflow:
+  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+  ret i1 false
+
+normal:
+  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+  ret i1 true
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)