[llvm-commits] [llvm] r63664 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Dale Johannesen
dalej at apple.com
Tue Feb 3 13:48:12 PST 2009
Author: johannes
Date: Tue Feb 3 15:48:12 2009
New Revision: 63664
URL: http://llvm.org/viewvc/llvm-project?rev=63664&view=rev
Log:
DebugLoc propgation
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=63664&r1=63663&r2=63664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Feb 3 15:48:12 2009
@@ -658,12 +658,13 @@
MemVT = SrcIsSSE ? SrcVT : DstVT;
SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
+ DebugLoc dl = N->getDebugLoc();
// FIXME: optimize the case where the src/dest is a load or store?
- SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
+ SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
N->getOperand(0),
MemTmp, NULL, 0, MemVT);
- SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
+ SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
NULL, 0, MemVT);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
@@ -729,6 +730,7 @@
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
bool is64Bit = Subtarget->is64Bit();
+ DebugLoc dl = N.getNode()->getDebugLoc();
DOUT << "MatchAddress: "; DEBUG(AM.dump());
// Limit recursion.
if (Depth > 5)
@@ -950,10 +952,11 @@
// Get the new AND mask, this folds to a constant.
SDValue X = Shift.getOperand(0);
- SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
+ SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
SDValue(C2, 0), SDValue(C1, 0));
- SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), X, NewANDMask);
- SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, N.getValueType(),
+ SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
+ NewANDMask);
+ SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
NewAND, SDValue(C1, 0));
// Insert the new nodes into the topological ordering.
@@ -1164,6 +1167,7 @@
assert(!Subtarget->is64Bit() &&
"getTruncateTo8Bit is only needed on x86-32!");
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+ DebugLoc dl = N0.getNode()->getDebugLoc();
// Ensure that the source register has an 8-bit subreg on 32-bit targets
unsigned Opc;
@@ -1180,8 +1184,8 @@
// The use of MVT::Flag here is not strictly accurate, but it helps
// scheduling in some cases.
- N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
- return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ N0 = SDValue(CurDAG->getTargetNode(Opc, dl, N0VT, MVT::Flag, N0), 0);
+ return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, N0, SRIdx, N0.getValue(1));
}
@@ -1195,7 +1199,8 @@
return NULL;
SDValue LSI = Node->getOperand(4); // MemOperand
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
- return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
+ return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
+ MVT::i32, MVT::i32, MVT::Other, Ops, 8);
}
SDNode *X86DAGToDAGISel::Select(SDValue N) {
@@ -1203,7 +1208,8 @@
MVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
-
+ DebugLoc dl = Node->getDebugLoc();
+
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
@@ -1288,13 +1294,13 @@
if (foldedLoad) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
@@ -1318,11 +1324,12 @@
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@@ -1405,13 +1412,13 @@
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
- Ops, 5), 0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
+ MVT::Other, Ops, 5), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
@@ -1423,10 +1430,11 @@
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
- SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
+ SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT),
+ 0);
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
ClrNode, InFlag).getValue(1);
}
@@ -1435,13 +1443,13 @@
if (foldedLoad) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
@@ -1465,11 +1473,13 @@
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
- CurDAG->getTargetConstant(8, MVT::i8)), 0);
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result,
+ CurDAG->getTargetConstant(8, MVT::i8)),
+ 0);
// Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@@ -1508,7 +1518,7 @@
break;
}
- SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, NVT, TruncOp);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -1563,7 +1573,7 @@
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
- return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
+ return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
MVT::Other, Ops, 3);
break;
}
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