[llvm-commits] Patch: PPC64 subregister moves

[Dan Gohman]

On Jan 29, 2009, at 11:36 PM, Burke, Max wrote:

> This attempts to reduce the number of emitted OR instructions used to
> move data in and out of subregisters on the PPC64 target. We've  
> noticed
> what looks like many extraneous register moves which in some cases are
> harmless, others which may have unintended, though minor, side effects
> (ie, mr 30, 30 blocking Cell PPE hardware thread at dispatch for 12
> cycles; mr 3, 3 changing the current hardware thread priority to  
> high).
> <ppc64moves.diff>_______________________________________________

I'm not very familiar with PowerPC, but this patch seems like a
reasonably good idea to me. I do have a few comments on it.

In this change:

  def : Pat<(i64 (zext GPRC:$in)),
-          (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
+        (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in,  
ppc_subreg_32bit), 0, 32)>;

For a zext, if this is really what the hardware provides, this should
use SUBREG_TO_REG with an (i64 0) for the first operand. See how this
is done on x86-64, for example.


In the *RegisterInfo.td file, registers that have subregs should be
declared with RegisterWithSubRegs, instead of just Register. This may
require changing some of the PPC-specific code at the top of the file.

Dan