[llvm-commits] [llvm] r63266 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bt.ll test/CodeGen/X86/commute-cmov.ll

[Dan Gohman]

On Jan 29, 2009, at 12:40 AM, Duncan Sands wrote:

> Hi Dan,
>
>>   case ISD::SRA:
>> +    // If this is an arithmetic shift right and only the low-bit  
>> is set, we can
>> +    // always convert this into a logical shr, even if the shift  
>> amount is
>> +    // variable.  The low bit of the shift cannot be an input sign  
>> bit unless
>> +    // the shift amount is >= the size of the datatype, which is  
>> undefined.
>> +    if (DemandedMask == 1)
>> +      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,  
>> Op.getValueType(),
>> +                                               Op.getOperand(0),  
>> Op.getOperand(1)));
>
> is this correct for MVT::i1?

Yes; the only valid shift count for MVT::i1 is 0.

>
>
>> +    // Simpify x&y == y to x&y == 0 if y has exactly one bit set.
>
> Simpify -> Simplify.  Also, the transform described in the comment
> looks wrong.  For example, suppose x==y.  Then the left version is
> equivalent to x == x, while the right version is equivalent to x == 0.

The code was right, but the comment was wrong. Both comment
errors are now fixed.

Thanks!

Dan