[llvm-commits] [llvm] r62768 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Bob Wilson
bob.wilson at apple.com
Thu Jan 22 09:39:32 PST 2009
Author: bwilson
Date: Thu Jan 22 11:39:32 2009
New Revision: 62768
URL: http://llvm.org/viewvc/llvm-project?rev=62768&view=rev
Log:
Add SelectionDAG::getNOT method to construct bitwise NOT operations,
corresponding to the "not" and "vnot" PatFrags. Use the new method
in some places where it seems appropriate.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jan 22 11:39:32 2009
@@ -366,6 +366,9 @@
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
+ /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
+ SDValue getNOT(SDValue Val, MVT VT);
+
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd).
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 22 11:39:32 2009
@@ -2759,15 +2759,15 @@
}
// fold select C, 0, X -> ~C & X
if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
- SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
- AddToWorkList(XORNode.getNode());
- return DAG.getNode(ISD::AND, VT, XORNode, N2);
+ SDValue NOTNode = DAG.getNOT(N0, VT);
+ AddToWorkList(NOTNode.getNode());
+ return DAG.getNode(ISD::AND, VT, NOTNode, N2);
}
// fold select C, X, 1 -> ~C | X
if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
- SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
- AddToWorkList(XORNode.getNode());
- return DAG.getNode(ISD::OR, VT, XORNode, N1);
+ SDValue NOTNode = DAG.getNOT(N0, VT);
+ AddToWorkList(NOTNode.getNode());
+ return DAG.getNode(ISD::OR, VT, NOTNode, N1);
}
// fold select C, X, 0 -> C & X
// FIXME: this should check for C type == X type, not i1?
@@ -5574,8 +5574,7 @@
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
N0);
- SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0,
- DAG.getConstant(~0ULL, XType));
+ SDValue NotN0 = DAG.getNOT(N0, XType);
return DAG.getNode(ISD::SRL, XType,
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
DAG.getConstant(XType.getSizeInBits()-1,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jan 22 11:39:32 2009
@@ -6318,7 +6318,7 @@
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
}
- Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
+ Op = DAG.getNOT(Op, VT);
return DAG.getNode(ISD::CTPOP, VT, Op);
}
case ISD::CTTZ: {
@@ -6327,9 +6327,7 @@
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
MVT VT = Op.getValueType();
- SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
- SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
- DAG.getNode(ISD::XOR, VT, Op, Tmp2),
+ SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jan 22 11:39:32 2009
@@ -816,6 +816,21 @@
getConstant(Imm, Op.getValueType()));
}
+/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
+///
+SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
+ SDValue NegOne;
+ if (VT.isVector()) {
+ MVT EltVT = VT.getVectorElementType();
+ SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
+ std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
+ NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size());
+ } else
+ NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
+
+ return getNode(ISD::XOR, VT, Val, NegOne);
+}
+
SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jan 22 11:39:32 2009
@@ -1798,39 +1798,39 @@
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: assert(0 && "Unknown integer setcc!");
- case ISD::SETEQ: // X == Y -> (X^Y)^1
+ case ISD::SETEQ: // X == Y -> ~(X^Y)
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
- N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
+ N0 = DAG.getNOT(Temp, MVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
break;
- case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
- case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
- Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
+ case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
+ case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
+ Temp = DAG.getNOT(N0, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
- case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
- case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
- Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
+ case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
+ case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
+ Temp = DAG.getNOT(N1, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
- case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
- case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
- Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
+ case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
+ case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
+ Temp = DAG.getNOT(N0, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
- case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
- case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
- Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
+ case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
+ case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
+ Temp = DAG.getNOT(N1, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
break;
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=62768&r1=62767&r2=62768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jan 22 11:39:32 2009
@@ -5253,14 +5253,9 @@
SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
// If the logical-not of the result is required, perform that now.
- if (Invert) {
- MVT EltVT = VT.getVectorElementType();
- SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
- std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
- SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
- NegOnes.size());
- Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
- }
+ if (Invert)
+ Result = DAG.getNOT(Result, VT);
+
return Result;
}
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