[llvm-commits] [llvm] r62691 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/pr3366.ll
Dan Gohman
gohman at apple.com
Wed Jan 21 06:50:16 PST 2009
Author: djg
Date: Wed Jan 21 08:50:16 2009
New Revision: 62691
URL: http://llvm.org/viewvc/llvm-project?rev=62691&view=rev
Log:
Fix a recent regression. ClrOpcode is not set for i8; for i8, if
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.
Added:
llvm/trunk/test/CodeGen/X86/pr3366.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=62691&r1=62690&r2=62691&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jan 21 08:50:16 2009
@@ -1381,9 +1381,10 @@
SDValue Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
+ bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
- if (NVT == MVT::i8 && !isSigned) {
+ if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
@@ -1405,7 +1406,7 @@
InFlag =
CurDAG->getCopyToReg(CurDAG->getEntryNode(),
LoReg, N0, SDValue()).getValue(1);
- if (isSigned && !CurDAG->SignBitIsZero(N0)) {
+ if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
Added: llvm/trunk/test/CodeGen/X86/pr3366.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3366.ll?rev=62691&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr3366.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr3366.ll Wed Jan 21 08:50:16 2009
@@ -0,0 +1,21 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep movzbl
+; PR3366
+
+define void @_ada_c34002a() nounwind {
+entry:
+ %0 = load i8* null, align 1
+ %1 = sdiv i8 90, %0
+ %2 = icmp ne i8 %1, 3
+ %3 = zext i1 %2 to i8
+ %toBool449 = icmp ne i8 %3, 0
+ %4 = or i1 false, %toBool449
+ %5 = zext i1 %4 to i8
+ %toBool450 = icmp ne i8 %5, 0
+ br i1 %toBool450, label %bb451, label %bb457
+
+bb451:
+ br label %bb457
+
+bb457:
+ unreachable
+}
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