[llvm-commits] [llvm] r62557 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/pr3216.ll

[Dan Gohman]

Author: djg
Date: Mon Jan 19 19:06:45 2009
New Revision: 62557

URL: http://llvm.org/viewvc/llvm-project?rev=62557&view=rev
Log:
Fix a dagcombine to not generate loads of non-round integer types,
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.

Added:
    llvm/trunk/test/CodeGen/X86/pr3216.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=62557&r1=62556&r2=62557&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 19 19:06:45 2009
@@ -3343,7 +3343,7 @@
 
   // Do not generate loads of non-round integer types since these can
   // be expensive (and would be wrong if the type is not byte sized).
-  if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
+  if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
       cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile()) {

Added: llvm/trunk/test/CodeGen/X86/pr3216.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3216.ll?rev=62557&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr3216.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr3216.ll Mon Jan 19 19:06:45 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep {sar.	\$5}
+
+ at foo = global i8 127
+
+define i32 @main() nounwind {
+entry:
+        %tmp = load i8* @foo
+        %bf.lo = lshr i8 %tmp, 5
+        %bf.lo.cleared = and i8 %bf.lo, 7
+        %0 = shl i8 %bf.lo.cleared, 5
+        %bf.val.sext = ashr i8 %0, 5
+        %conv = sext i8 %bf.val.sext to i32
+        ret i32 %conv
+}