[llvm-commits] [llvm] r62505 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Bill Wendling]

Gracias!

-bw

On Jan 19, 2009, at 12:19 AM, Evan Cheng <evan.cheng at apple.com> wrote:

> Author: evancheng
> Date: Mon Jan 19 02:19:57 2009
> New Revision: 62505
>
> URL: http://llvm.org/viewvc/llvm-project?rev=62505&view=rev
> Log:
> Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector)  
> has two uses so we should make it the second source operand of  
> ISD::OR so 2-address pass won't have to be smart about commuting.
>
> %reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8)  
> [ConstantPool + 0]
> %reg1025<def> = MOVSD2PDrr %reg1024
> %reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16)  
> [FixedStack-1 + 0]
> %reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
> %reg1028<def> = MOVPD2SDrr %reg1027<kill>
> %reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
> %reg1030<def> = CVTSD2SSrr %reg1029<kill>
> MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4)  
> [FixedStack0 + 0]
> %reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16)  
> [FixedStack0 + 0]
> RET %reg1031<kill>, %ST0<imp-use,kill>
>
> The reason 2-addr pass isn't smart enough to commute the ORPSrr is  
> because it can't look pass the MOVSD2PDrr instruction.
>
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=62505&r1=62504&r2=62505&view=diff
>
> === 
> === 
> === 
> =====================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 19  
> 02:19:57 2009
> @@ -4858,10 +4858,10 @@
>   SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64,
>                            DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
>                                         
> DAG.getNode(ISD::SCALAR_TO_VECTOR,
> -                                                   MVT::v2f64,  
> Bias)),
> +                                                   MVT::v2f64,  
> Load)),
>                            DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
>                                         
> DAG.getNode(ISD::SCALAR_TO_VECTOR,
> -                                                   MVT::v2f64,  
> Load)));
> +                                                   MVT::v2f64,  
> Bias)));
>   Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
>                    DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or),
>                    DAG.getIntPtrConstant(0));
>
>
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