[llvm-commits] [llvm] r62413 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/lea-3.ll test/CodeGen/X86/lea-4.ll

[Evan Cheng]

Author: evancheng
Date: Sat Jan 17 01:09:27 2009
New Revision: 62413

URL: http://llvm.org/viewvc/llvm-project?rev=62413&view=rev
Log:
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.

Added:
    llvm/trunk/test/CodeGen/X86/lea-4.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/lea-3.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=62413&r1=62412&r2=62413&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Jan 17 01:09:27 2009
@@ -817,7 +817,7 @@
           AM.IndexReg = ShVal.getNode()->getOperand(0);
           ConstantSDNode *AddVal =
             cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
-          uint64_t Disp = AM.Disp + (AddVal->getZExtValue() << Val);
+          uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
           if (!is64Bit || isInt32(Disp))
             AM.Disp = Disp;
           else
@@ -858,7 +858,7 @@
             Reg = MulVal.getNode()->getOperand(0);
             ConstantSDNode *AddVal =
               cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
-            uint64_t Disp = AM.Disp + AddVal->getZExtValue() *
+            uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
                                       CN->getZExtValue();
             if (!is64Bit || isInt32(Disp))
               AM.Disp = Disp;
@@ -874,19 +874,18 @@
     }
     break;
 
-  case ISD::ADD:
-    {
-      X86ISelAddressMode Backup = AM;
-      if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
-          !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
-        return false;
-      AM = Backup;
-      if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
-          !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
-        return false;
-      AM = Backup;
-    }
+  case ISD::ADD: {
+    X86ISelAddressMode Backup = AM;
+    if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
+        !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
+      return false;
+    AM = Backup;
+    if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
+        !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
+      return false;
+    AM = Backup;
     break;
+  }
 
   case ISD::OR:
     // Handle "X | C" as "X + C" iff X is known to have C bits clear.

Modified: llvm/trunk/test/CodeGen/X86/lea-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea-3.ll?rev=62413&r1=62412&r2=62413&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea-3.ll Sat Jan 17 01:09:27 2009
@@ -1,4 +1,3 @@
-
 ; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal	(%rdi,%rdi,2), %eax}
 define i32 @test(i32 %a) {
         %tmp2 = mul i32 %a, 3           ; <i32> [#uses=1]

Added: llvm/trunk/test/CodeGen/X86/lea-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea-4.ll?rev=62413&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea-4.ll (added)
+++ llvm/trunk/test/CodeGen/X86/lea-4.ll Sat Jan 17 01:09:27 2009
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep lea | count 2
+
+define zeroext i16 @t1(i32 %on_off) nounwind {
+entry:
+	%0 = sub i32 %on_off, 1
+	%1 = mul i32 %0, 2
+	%2 = trunc i32 %1 to i16
+	%3 = zext i16 %2 to i32
+	%4 = trunc i32 %3 to i16
+	ret i16 %4
+}
+
+define i32 @t2(i32 %on_off) nounwind {
+entry:
+	%0 = sub i32 %on_off, 1
+	%1 = mul i32 %0, 2
+        %2 = and i32 %1, 65535
+	ret i32 %2
+}