[llvm-commits] [llvm] r62177 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/Generic/2006-07-03-schedulers.ll test/CodeGen/Mips/2008-07-23-fpcmp.ll

[Dan Gohman]

Author: djg
Date: Tue Jan 13 14:24:13 2009
New Revision: 62177

URL: http://llvm.org/viewvc/llvm-project?rev=62177&view=rev
Log:
The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=62177&r1=62176&r2=62177&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Jan 13 14:24:13 2009
@@ -140,8 +140,12 @@
 
   // Top down: release successors.
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I)
+       I != E; ++I) {
+    assert(!I->isAssignedRegDep() &&
+           "The list-td scheduler doesn't yet support physreg dependencies!");
+
     ReleaseSucc(SU, *I);
+  }
 
   SU->isScheduled = true;
   AvailableQueue->ScheduledNode(SU);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=62177&r1=62176&r2=62177&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Jan 13 14:24:13 2009
@@ -816,8 +816,12 @@
 
   // Top down: release successors
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I)
+       I != E; ++I) {
+    assert(!I->isAssignedRegDep() &&
+           "The list-tdrr scheduler doesn't yet support physreg dependencies!");
+
     ReleaseSucc(SU, &*I);
+  }
 
   SU->isScheduled = true;
   AvailableQueue->ScheduledNode(SU);

Modified: llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll?rev=62177&r1=62176&r2=62177&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll Tue Jan 13 14:24:13 2009
@@ -1,10 +1,11 @@
 ; RUN: llvm-as < %s | llc -pre-RA-sched=default
-; RUN: llvm-as < %s | llc -pre-RA-sched=list-td
-; RUN: llvm-as < %s | llc -pre-RA-sched=list-tdrr
 ; RUN: llvm-as < %s | llc -pre-RA-sched=list-burr
 ; RUN: llvm-as < %s | llc -pre-RA-sched=fast
 ; PR859
 
+; The top-down schedulers are excluded here because they don't yet support
+; targets that use physreg defs.
+
 declare i32 @printf(i8*, i32, float)
 
 define i32 @testissue(i32 %i, float %x, float %y) {

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll?rev=62177&r1=62176&r2=62177&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll Tue Jan 13 14:24:13 2009
@@ -1,6 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=mips -f -o %t
 ; RUN: grep {c\\..*\\.s} %t | count 3
 ; RUN: grep {bc1\[tf\]} %t | count 3
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-psp-elf"