[llvm-commits] [llvm] r61129 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Duncan Sands]

Hi Mon Ping,

> Fix expansion of vsetcc to set the high bit for true instead of 1.
...
>          SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
>                                    Tmp1, DAG.getIntPtrConstant(i));
>          Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
> -                              DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
> -                                          Tmp2, DAG.getIntPtrConstant(i)),
> -                              CC);
> -        Ops[i] = DAG.getNode(ISD::SIGN_EXTEND, EltVT, Ops[i]);
> +                             DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
> +                                         Tmp2, DAG.getIntPtrConstant(i)),
> +                             CC);
> +        Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
> +                             DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
> +                             DAG.getConstant(0, EltVT));

wouldn't it make more sense to use a SELECT_CC rather than a SETCC+SELECT pair?

Ciao,

Duncan.