[llvm-commits] [llvm] r61425 - in /llvm/trunk/lib/Target/X86: X86Instr64bit.td X86InstrInfo.td

[Chris Lattner]

Author: lattner
Date: Wed Dec 24 19:32:49 2008
New Revision: 61425

URL: http://llvm.org/viewvc/llvm-project?rev=61425&view=rev
Log:
Fix some JIT encodings.

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=61425&r1=61424&r2=61425&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Dec 24 19:32:49 2008
@@ -921,14 +921,14 @@
 // TODO: BT with immediate operands.
 // TODO: BTC, BTR, and BTS
 let Defs = [EFLAGS] in {
-def BT64rr : RI<0xA3, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
                "bt{q}\t{$src2, $src1|$src1, $src2}",
                [(X86bt GR64:$src1, GR64:$src2),
-                (implicit EFLAGS)]>;
-def BT64mr : RI<0xA3, MRMSrcMem, (outs), (ins i64mem:$src1, GR64:$src2),
+                (implicit EFLAGS)]>, TB;
+def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
                "bt{q}\t{$src2, $src1|$src1, $src2}",
                [(X86bt (loadi64 addr:$src1), GR64:$src2),
-                (implicit EFLAGS)]>;
+                (implicit EFLAGS)]>, TB;
 } // Defs = [EFLAGS]
 
 // Conditional moves

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=61425&r1=61424&r2=61425&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Dec 24 19:32:49 2008
@@ -2658,19 +2658,19 @@
 def BT16rr : I<0xA3, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
                "bt{w}\t{$src2, $src1|$src1, $src2}",
                [(X86bt GR16:$src1, GR16:$src2),
-                (implicit EFLAGS)]>, OpSize;
+                (implicit EFLAGS)]>, OpSize, TB;
 def BT32rr : I<0xA3, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
                "bt{l}\t{$src2, $src1|$src1, $src2}",
                [(X86bt GR32:$src1, GR32:$src2),
-                (implicit EFLAGS)]>;
-def BT16mr : I<0xA3, MRMSrcMem, (outs), (ins i16mem:$src1, GR16:$src2),
+                (implicit EFLAGS)]>, TB;
+def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
                "bt{w}\t{$src2, $src1|$src1, $src2}",
                [(X86bt (loadi16 addr:$src1), GR16:$src2),
-                (implicit EFLAGS)]>, OpSize;
-def BT32mr : I<0xA3, MRMSrcMem, (outs), (ins i32mem:$src1, GR32:$src2),
+                (implicit EFLAGS)]>, OpSize, TB;
+def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
                "bt{l}\t{$src2, $src1|$src1, $src2}",
                [(X86bt (loadi32 addr:$src1), GR32:$src2),
-                (implicit EFLAGS)]>;
+                (implicit EFLAGS)]>, TB;
 } // Defs = [EFLAGS]
 
 // Sign/Zero extenders