[llvm-commits] [llvm] r61119 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp test/CodeGen/X86/2008-12-16-BadShift.ll

[Eli Friedman]

Author: efriedma
Date: Tue Dec 16 21:35:17 2008
New Revision: 61119

URL: http://llvm.org/viewvc/llvm-project?rev=61119&view=rev
Log:
Fix for PR3225: disable a broken optimization in
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

In terms of restoring the optimization, the best fix here isn't 
obvious... any ideas?


Added:
    llvm/trunk/test/CodeGen/X86/2008-12-16-BadShift.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=61119&r1=61118&r2=61119&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Dec 16 21:35:17 2008
@@ -1211,6 +1211,8 @@
     }
   }
 
+#if 0
+  // FIXME: This code is broken for shifts with a zero amount!
   // If we know that all of the high bits of the shift amount are zero, then we
   // can do this as a couple of simple shifts.
   if ((KnownZero & HighBitMask) == HighBitMask) {
@@ -1232,6 +1234,7 @@
                      DAG.getNode(Op2, NVT, InL, Amt2));
     return true;
   }
+#endif
 
   return false;
 }

Added: llvm/trunk/test/CodeGen/X86/2008-12-16-BadShift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-12-16-BadShift.ll?rev=61119&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-12-16-BadShift.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-12-16-BadShift.ll Tue Dec 16 21:35:17 2008
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc | not grep shrl
+; Note: this test is really trying to make sure that the shift
+; returns the right result; shrl is most likely wrong,
+; but if CodeGen starts legitimately using an shrl here,
+; please adjust the test appropriately.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+ at .str = internal constant [6 x i8] c"%lld\0A\00"		; <[6 x i8]*> [#uses=1]
+
+define i64 @mebbe_shift(i32 %xx, i32 %test) nounwind {
+entry:
+	%conv = zext i32 %xx to i64		; <i64> [#uses=1]
+	%tobool = icmp ne i32 %test, 0		; <i1> [#uses=1]
+	%shl = select i1 %tobool, i64 3, i64 0		; <i64> [#uses=1]
+	%x.0 = shl i64 %conv, %shl		; <i64> [#uses=1]
+	ret i64 %x.0
+}
+