[llvm-commits] [llvm] r61063 - /llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h

[Dan Gohman]

Author: djg
Date: Mon Dec 15 18:48:53 2008
New Revision: 61063

URL: http://llvm.org/viewvc/llvm-project?rev=61063&view=rev
Log:
Reorder some SDep methods. No functionality change.

Modified:
    llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h

Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=61063&r1=61062&r2=61063&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Mon Dec 15 18:48:53 2008
@@ -166,12 +166,6 @@
       return getKind() != Data;
     }
 
-    /// isArtificial - Test if this is an Order dependence that is marked
-    /// as "artificial", meaning it isn't necessary for correctness.
-    bool isArtificial() const {
-      return getKind() == Order && Contents.Order.isArtificial;
-    }
-
     /// isMustAlias - Test if this is an Order dependence that is marked
     /// as "must alias", meaning that the SUnits at either end of the edge
     /// have a memory dependence on a known memory location.
@@ -179,6 +173,12 @@
       return getKind() == Order && Contents.Order.isMustAlias;
     }
 
+    /// isArtificial - Test if this is an Order dependence that is marked
+    /// as "artificial", meaning it isn't necessary for correctness.
+    bool isArtificial() const {
+      return getKind() == Order && Contents.Order.isArtificial;
+    }
+
     /// isAssignedRegDep - Test if this is a Data dependence that is
     /// associated with a register.
     bool isAssignedRegDep() const {