[llvm-commits] [llvm] r60844 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp

[Bill Wendling]

Author: void
Date: Wed Dec 10 13:44:24 2008
New Revision: 60844

URL: http://llvm.org/viewvc/llvm-project?rev=60844&view=rev
Log:
Only perform SETO/SETC to JO/JC conversion if extractvalue is coming from an arithmetic with overflow instruction.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=60844&r1=60843&r2=60844&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Dec 10 13:44:24 2008
@@ -763,52 +763,67 @@
     // looking for the SETO/SETC instruction. If an instruction modifies the
     // EFLAGS register before we reach the SETO/SETC instruction, then we can't
     // convert the branch into a JO/JC instruction.
-    const MachineInstr *SetMI = 0;
-    unsigned Reg = lookUpRegForValue(EI);
 
-    for (MachineBasicBlock::const_reverse_iterator
-           RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
-      const MachineInstr &MI = *RI;
-
-      if (MI.modifiesRegister(Reg)) {
-        unsigned Src, Dst;
-
-        if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) {
-          Reg = Src;
-          continue;
-        }
-
-        SetMI = &MI;
-        break;
-      }
+    Value *Agg = EI->getAggregateOperand();
 
-      const TargetInstrDesc &TID = MI.getDesc();
-      const unsigned *ImpDefs = TID.getImplicitDefs();
+    if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
+      Function *F = CI->getCalledFunction();
 
-      if (TID.hasUnmodeledSideEffects()) break;
+      if (F && F->isDeclaration()) {
+        switch (F->getIntrinsicID()) {
+        default: break;
+        case Intrinsic::sadd_with_overflow:
+        case Intrinsic::uadd_with_overflow: {
+          const MachineInstr *SetMI = 0;
+          unsigned Reg = lookUpRegForValue(EI);
+
+          for (MachineBasicBlock::const_reverse_iterator
+                 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
+            const MachineInstr &MI = *RI;
+
+            if (MI.modifiesRegister(Reg)) {
+              unsigned Src, Dst;
+
+              if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) {
+                Reg = Src;
+                continue;
+              }
+
+              SetMI = &MI;
+              break;
+            }
+
+            const TargetInstrDesc &TID = MI.getDesc();
+            const unsigned *ImpDefs = TID.getImplicitDefs();
+
+            if (TID.hasUnmodeledSideEffects()) break;
+
+            bool ModifiesEFlags = false;
+
+            if (ImpDefs) {
+              for (unsigned u = 0; ImpDefs[u]; ++u)
+                if (ImpDefs[u] == X86::EFLAGS) {
+                  ModifiesEFlags = true;
+                  break;
+                }
+            }
 
-      bool ModifiesEFlags = false;
-
-      if (ImpDefs) {
-        for (unsigned u = 0; ImpDefs[u]; ++u)
-          if (ImpDefs[u] == X86::EFLAGS) {
-            ModifiesEFlags = true;
-            break;
+            if (ModifiesEFlags) break;
           }
-      }
 
-      if (ModifiesEFlags) break;
-    }
+          if (SetMI) {
+            unsigned OpCode = SetMI->getOpcode();
 
-    if (SetMI) {
-      unsigned OpCode = SetMI->getOpcode();
-
-      if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
-        BuildMI(MBB, TII.get((OpCode == X86::SETOr) ? 
-                             X86::JO : X86::JC)).addMBB(TrueMBB);
-        FastEmitBranch(FalseMBB);
-        MBB->addSuccessor(TrueMBB);
-        return true;
+            if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
+              BuildMI(MBB, TII.get((OpCode == X86::SETOr) ? 
+                                   X86::JO : X86::JC)).addMBB(TrueMBB);
+              FastEmitBranch(FalseMBB);
+              MBB->addSuccessor(TrueMBB);
+              return true;
+            }
+          }
+        }
+        }
       }
     }
   }