[llvm-commits] [llvm] r60740 - in /llvm/trunk: docs/LangRef.html lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/vshift_split.ll
Mon P Wang
wangmp at apple.com
Mon Dec 8 21:46:40 PST 2008
Author: wangmp
Date: Mon Dec 8 23:46:39 2008
New Revision: 60740
URL: http://llvm.org/viewvc/llvm-project?rev=60740&view=rev
Log:
Fix getNode to allow a vector for the shift amount for shifts of vectors.
Fix the shift amount when unrolling a vector shift into scalar shifts.
Fix problem in getShuffleScalarElt where it assumes that the input of
a bit convert must be a vector.
Added:
llvm/trunk/test/CodeGen/X86/vshift_split.ll
Modified:
llvm/trunk/docs/LangRef.html
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=60740&r1=60739&r2=60740&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Dec 8 23:46:39 2008
@@ -2591,6 +2591,7 @@
<result> = shl i32 4, 2 <i>; yields {i32}: 16</i>
<result> = shl i32 1, 10 <i>; yields {i32}: 1024</i>
<result> = shl i32 1, 32 <i>; undefined</i>
+ <result> = shl <2 x i32> < i32 1, i32 1>, < i32 1, i32 2> <i>; yields: result=<2 x i32> < i32 2, i32 4></i>
</pre>
</div>
<!-- _______________________________________________________________________ -->
@@ -2624,6 +2625,7 @@
<result> = lshr i8 4, 3 <i>; yields {i8}:result = 0</i>
<result> = lshr i8 -2, 1 <i>; yields {i8}:result = 0x7FFFFFFF </i>
<result> = lshr i32 1, 32 <i>; undefined</i>
+ <result> = lshr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 2> <i>; yields: result=<2 x i32> < i32 0x7FFFFFFF, i32 1></i>
</pre>
</div>
@@ -2659,6 +2661,7 @@
<result> = ashr i8 4, 3 <i>; yields {i8}:result = 0</i>
<result> = ashr i8 -2, 1 <i>; yields {i8}:result = -1</i>
<result> = ashr i32 1, 32 <i>; undefined</i>
+ <result> = ashr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 3> <i>; yields: result=<2 x i32> < i32 -1, i32 0></i>
</pre>
</div>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=60740&r1=60739&r2=60740&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 8 23:46:39 2008
@@ -297,6 +297,9 @@
SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
+
+ // Returns the legalized (truncated or extended) shift amount.
+ SDValue LegalizeShiftAmount(SDValue ShiftAmt);
};
}
@@ -786,8 +789,19 @@
Operands[j] = Operand;
}
}
- Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
- &Operands[0], Operands.size()));
+
+ switch (Op.getOpcode()) {
+ default:
+ Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
+ &Operands[0], Operands.size()));
+ break;
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
+ LegalizeShiftAmount(Operands[1])));
+ break;
+ }
}
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
@@ -850,6 +864,17 @@
PseudoSourceValue::getFixedStack(SPFI), 0);
}
+SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
+ if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
+ return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
+
+ if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
+ return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+
+ return ShiftAmt;
+}
+
+
/// LegalizeOp - We know that the specified value has a legal type, and
/// that its operands are legal. Now ensure that the operation itself
/// is legal, recursively ensuring that the operands' operations remain
@@ -3094,11 +3119,8 @@
Node->getOpcode() == ISD::SRL ||
Node->getOpcode() == ISD::SRA) &&
!Node->getValueType(0).isVector()) {
- if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
- Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
- else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
- Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
- }
+ Tmp2 = LegalizeShiftAmount(Tmp2);
+ }
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=60740&r1=60739&r2=60740&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Dec 8 23:46:39 2008
@@ -2066,7 +2066,8 @@
if (V.getOpcode() == ISD::BIT_CONVERT) {
V = V.getOperand(0);
- if (V.getValueType().getVectorNumElements() != NumElems)
+ MVT VVT = V.getValueType();
+ if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems)
return SDValue();
}
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
@@ -2418,7 +2419,8 @@
"Shift operators return type must be the same as their first arg");
assert(VT.isInteger() && N2.getValueType().isInteger() &&
"Shifts only work on integers");
- assert(N2.getValueType() == TLI.getShiftAmountTy() &&
+ assert((N2.getValueType() == TLI.getShiftAmountTy() ||
+ (N2.getValueType().isVector() && N2.getValueType().isInteger())) &&
"Wrong type for shift amount");
// Always fold shifts of i1 values so the code generator doesn't need to
Added: llvm/trunk/test/CodeGen/X86/vshift_split.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift_split.ll?rev=60740&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift_split.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vshift_split.ll Mon Dec 8 23:46:39 2008
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %shr
+}
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