[llvm-commits] [llvm] r60459 - in /llvm/trunk: lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMRegisterInfo.cpp lib/Target/Alpha/AlphaInstrInfo.td lib/Target/PowerPC/PPCHazardRecognizers.cpp lib/Target/PowerPC/PPCInstr64Bit.td lib/Target/PowerPC/PPCInstrInfo.td utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/DAGISelEmitter.cpp
Dan Gohman
gohman at apple.com
Tue Dec 2 18:30:18 PST 2008
Author: djg
Date: Tue Dec 2 20:30:17 2008
New Revision: 60459
URL: http://llvm.org/viewvc/llvm-project?rev=60459&view=rev
Log:
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
Modified:
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Dec 2 20:30:17 2008
@@ -414,7 +414,7 @@
const TargetInstrDesc &TID = I->getDesc();
if (TID.isCall())
Time += 10;
- else if (TID.isSimpleLoad() || TID.mayStore())
+ else if (TID.mayLoad() || TID.mayStore())
Time += 2;
else
++Time;
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Tue Dec 2 20:30:17 2008
@@ -834,7 +834,7 @@
assert(Offset && "This code isn't needed if offset already handled!");
if (isThumb) {
- if (Desc.isSimpleLoad()) {
+ if (Desc.mayLoad()) {
// Use the destination register to materialize sp + offset.
unsigned TmpReg = MI.getOperand(0).getReg();
bool UseRR = false;
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Tue Dec 2 20:30:17 2008
@@ -570,7 +570,9 @@
//load address, rellocated gpdist form
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
+let OutOperandList = (ops GPRC:$RA),
+ InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
+ mayLoad = 1 in {
def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
}
@@ -589,7 +591,9 @@
def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
}
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
+let OutOperandList = (ops GPRC:$RA),
+ InOperandList = (ops s64imm:$DISP, GPRC:$RB),
+ mayLoad = 1 in {
def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Tue Dec 2 20:30:17 2008
@@ -72,7 +72,7 @@
const TargetInstrDesc &TID = TII.get(Opcode);
- isLoad = TID.isSimpleLoad();
+ isLoad = TID.mayLoad();
isStore = TID.mayStore();
unsigned TSFlags = TID.TSFlags;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Dec 2 20:30:17 2008
@@ -487,6 +487,7 @@
PPC970_DGroup_Cracked;
// Update forms.
+let mayLoad = 1 in
def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
ptr_rc:$rA),
"lhau $rD, $disp($rA)", LdStGeneral,
@@ -520,6 +521,7 @@
// Update forms.
+let mayLoad = 1 in {
def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
"lbzu $rD, $addr", LdStGeneral,
[]>, RegConstraint<"$addr.reg = $ea_result">,
@@ -533,6 +535,7 @@
[]>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">;
}
+}
// Full 8-byte loads.
@@ -544,6 +547,7 @@
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
+let mayLoad = 1 in
def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
"ldu $rD, $addr", LdStLD,
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Dec 2 20:30:17 2008
@@ -683,6 +683,7 @@
// Unindexed (r+i) Loads with Update (preinc).
+let mayLoad = 1 in {
def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
"lbzu $rD, $addr", LdStGeneral,
[]>, RegConstraint<"$addr.reg = $ea_result">,
@@ -713,6 +714,7 @@
[]>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">;
}
+}
// Indexed (r+r) Loads.
//
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Dec 2 20:30:17 2008
@@ -1759,6 +1759,15 @@
MayLoad = true;
}
+ // Sanity-check the isSimpleLoad flag.
+ if (Inst.isSimpleLoad) {
+ if (!MayLoad)
+ fprintf(stderr,
+ "Warning: mayLoad flag not set or inferred for instruction '%s'"
+ " which has isSimpleLoad set.\n",
+ Inst.TheDef->getName().c_str());
+ }
+
if (Inst.neverHasSideEffects) {
if (HadPattern)
fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=60459&r1=60458&r2=60459&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Dec 2 20:30:17 2008
@@ -1097,7 +1097,7 @@
// Generate MemOperandSDNodes nodes for each memory accesses covered by
// this pattern.
- if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
+ if (II.mayLoad | II.mayStore) {
std::vector<std::string>::const_iterator mi, mie;
for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
std::string LSIName = "LSI_" + *mi;
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