[llvm-commits] [llvm] r60123 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrInfo.cpp X86InstrInfo.h X86InstrInfo.td
Evan Cheng
evan.cheng at apple.com
Wed Nov 26 14:57:42 PST 2008
Bill, I don't think this is the right approach. Details in private
email.
Evan
On Nov 26, 2008, at 2:37 PM, Bill Wendling wrote:
> Author: void
> Date: Wed Nov 26 16:37:40 2008
> New Revision: 60123
>
> URL: http://llvm.org/viewvc/llvm-project?rev=60123&view=rev
> Log:
> Generate something sensible for an [SU]ADDO op when the overflow/
> carry flag is
> the conditional for the BRCOND statement. For instance, it will
> generate:
>
> addl %eax, %ecx
> jo LOF
>
> instead of
>
> addl %eax, %ecx
> ; About 10 instructions to compare the signs of LHS, RHS, and sum.
> jl LOF
>
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=60123&r1=60122&r2=60123&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 26
> 16:37:40 2008
> @@ -6150,6 +6150,26 @@
>
> SDValue X86TargetLowering::LowerXADDO(SDValue Op, SelectionDAG &DAG,
> ISD::NodeType NTy) {
> + SDNode *N = Op.getNode();
> +
> + for (SDNode::use_iterator I = N->use_begin(), E = N->use_end();
> I != E; ++I) {
> + SDNode *UseNode = *I;
> +
> + if (UseNode->getOpcode() == ISD::BRCOND) {
> + // Lower a branch on the overflow/carry flag into a "JO"/"JC"
> + // instruction. Convert the addition into an actual addition,
> not just a
> + // pseudo node.
> + SDValue LHS = N->getOperand(0);
> + SDValue RHS = N->getOperand(1);
> + SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS,
> RHS);
> +
> + SDValue Ops[] = { UseNode->getOperand(2), UseNode-
> >getOperand(0) };
> + DAG.SelectNodeTo(UseNode, (NTy == ISD::SADDO) ? X86::JO :
> X86::JC,
> + MVT::Other, Ops, 2);
> + return Sum;
> + }
> + }
> +
> return SDValue();
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=60123&r1=60122&r2=60123&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Nov 26 16:37:40
> 2008
> @@ -1382,6 +1382,8 @@
> case X86::JNP: return X86::COND_NP;
> case X86::JO: return X86::COND_O;
> case X86::JNO: return X86::COND_NO;
> + case X86::JC: return X86::COND_C;
> + case X86::JNC: return X86::COND_NC;
> }
> }
>
> @@ -1404,6 +1406,8 @@
> case X86::COND_NP: return X86::JNP;
> case X86::COND_O: return X86::JO;
> case X86::COND_NO: return X86::JNO;
> + case X86::COND_C: return X86::JC;
> + case X86::COND_NC: return X86::JNC;
> }
> }
>
> @@ -1428,6 +1432,8 @@
> case X86::COND_NP: return X86::COND_P;
> case X86::COND_O: return X86::COND_NO;
> case X86::COND_NO: return X86::COND_O;
> + case X86::COND_C: return X86::COND_NC;
> + case X86::COND_NC: return X86::COND_C;
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=60123&r1=60122&r2=60123&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Wed Nov 26 16:37:40 2008
> @@ -41,9 +41,11 @@
> COND_NO = 10,
> COND_NP = 11,
> COND_NS = 12,
> - COND_O = 13,
> - COND_P = 14,
> - COND_S = 15,
> + COND_NC = 13,
> + COND_O = 14,
> + COND_P = 15,
> + COND_S = 16,
> + COND_C = 17,
>
> // Artificial condition codes. These are used by AnalyzeBranch
> // to indicate a block terminated with two conditional branches to
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=60123&r1=60122&r2=60123&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Nov 26 16:37:40 2008
> @@ -235,9 +235,11 @@
> def X86_COND_NO : PatLeaf<(i8 10)>;
> def X86_COND_NP : PatLeaf<(i8 11)>;
> def X86_COND_NS : PatLeaf<(i8 12)>;
> -def X86_COND_O : PatLeaf<(i8 13)>;
> -def X86_COND_P : PatLeaf<(i8 14)>;
> -def X86_COND_S : PatLeaf<(i8 15)>;
> +def X86_COND_NC : PatLeaf<(i8 13)>;
> +def X86_COND_O : PatLeaf<(i8 14)>;
> +def X86_COND_P : PatLeaf<(i8 15)>;
> +def X86_COND_S : PatLeaf<(i8 16)>;
> +def X86_COND_C : PatLeaf<(i8 17)>;
>
> def i16immSExt8 : PatLeaf<(i16 imm), [{
> // i16immSExt8 predicate - True if the 16-bit immediate fits in a
> 8-bit
> @@ -449,6 +451,10 @@
> [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
> def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
> [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
> +def JC : IBr<0x82, (ins brtarget:$dst), "jc\t$dst",
> + [(X86brcond bb:$dst, X86_COND_C, EFLAGS)]>, TB;
> +def JNC : IBr<0x83, (ins brtarget:$dst), "jnc\t$dst",
> + [(X86brcond bb:$dst, X86_COND_NC, EFLAGS)]>, TB;
> } // Uses = [EFLAGS]
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
>
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