[llvm-commits] [llvm] r60120 - in /llvm/trunk: lib/Transforms/Scalar/CodeGenPrepare.cpp test/CodeGen/X86/isel-sink3.ll

[Chris Lattner]

Author: lattner
Date: Wed Nov 26 16:16:44 2008
New Revision: 60120

URL: http://llvm.org/viewvc/llvm-project?rev=60120&view=rev
Log:
Turn on my codegen prepare heuristic by default.  It doesn't affect 
performance in most cases on the Grawp tester, but does speed some 
things up (like shootout/hash by 15%).  This also doesn't impact 
compile time in a noticable way on the Grawp tester.

It also, of course, gets the testcase it was designed for right :)

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
    llvm/trunk/test/CodeGen/X86/isel-sink3.ll

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=60120&r1=60119&r2=60120&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed Nov 26 16:16:44 2008
@@ -1025,10 +1025,6 @@
 
 
 
-#include "llvm/Support/CommandLine.h"
-cl::opt<bool> ENABLECRAZYHACK("enable-smarter-addr-folding", cl::Hidden);
-
-
 /// IsProfitableToFoldIntoAddressingMode - It is possible for the addressing
 /// mode of the machine to fold the specified instruction into a load or store
 /// that ultimately uses it.  However, the specified instruction has multiple
@@ -1053,7 +1049,7 @@
 bool AddressingModeMatcher::
 IsProfitableToFoldIntoAddressingMode(Instruction *I, ExtAddrMode &AMBefore,
                                      ExtAddrMode &AMAfter) {
-  if (IgnoreProfitability || !ENABLECRAZYHACK) return true;
+  if (IgnoreProfitability) return true;
   
   // AMBefore is the addressing mode before this instruction was folded into it,
   // and AMAfter is the addressing mode after the instruction was folded.  Get

Modified: llvm/trunk/test/CodeGen/X86/isel-sink3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/isel-sink3.ll?rev=60120&r1=60119&r2=60120&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/isel-sink3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/isel-sink3.ll Wed Nov 26 16:16:44 2008
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -enable-smarter-addr-folding | grep {addl.(%eax), %ecx}
-; RUN: llvm-as < %s | llc -enable-smarter-addr-folding | not grep leal
+; RUN: llvm-as < %s | llc | grep {addl.(%eax), %ecx}
+; RUN: llvm-as < %s | llc | not grep leal
 ; this should not sink %1 into bb1, that would increase reg pressure.
 
 ; rdar://6399178