[llvm-commits] [llvm] r59971 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeDAG.cpp CodeGen/SelectionDAG/SelectionDAGBuild.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h

Bill Wendling isanbard at gmail.com
Mon Nov 24 11:21:49 PST 2008


Author: void
Date: Mon Nov 24 13:21:46 2008
New Revision: 59971

URL: http://llvm.org/viewvc/llvm-project?rev=59971&view=rev
Log:
- Make lowering of "add with overflow" customizable by back-ends.
- Mark "add with overflow" as having a custom lowering for X86. Give it a null
  lowering representation for now.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=59971&r1=59970&r2=59971&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 24 13:21:46 2008
@@ -4172,22 +4172,34 @@
 
   case ISD::SADDO:
   case ISD::UADDO: {
-    SDValue LHS = LegalizeOp(Node->getOperand(0));
-    SDValue RHS = LegalizeOp(Node->getOperand(1));
+    MVT VT = Node->getValueType(0);
+    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
+    default: assert(0 && "This action not supported for this op yet!");
+    case TargetLowering::Custom:
+      Result = TLI.LowerOperation(Op, DAG);
+      if (Result.getNode()) break;
+      // FALLTHROUGH
+    case TargetLowering::Legal: {
+      SDValue LHS = LegalizeOp(Node->getOperand(0));
+      SDValue RHS = LegalizeOp(Node->getOperand(1));
+
+      SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
+      MVT OType = Node->getValueType(1);
+      SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
+                                 (Node->getOpcode() == ISD::SADDO) ?
+                                 ISD::SETLT : ISD::SETULT);
+
+      MVT ValueVTs[] = { LHS.getValueType(), OType };
+      SDValue Ops[] = { Sum, Cmp };
+
+      Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
+      SDNode *RNode = Result.getNode();
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
+      break;
+    }
+    }
 
-    SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
-    MVT OType = SDValue(Node, 1).getValueType();
-    SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
-                               (Node->getOpcode() == ISD::SADDO) ?
-                               ISD::SETLT : ISD::SETULT);
-
-    MVT ValueVTs[] = { LHS.getValueType(), OType };
-    SDValue Ops[] = { Sum, Cmp };
-
-    Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
-    SDNode *RNode = Result.getNode();
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
     break;
   }
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=59971&r1=59970&r2=59971&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Nov 24 13:21:46 2008
@@ -4096,9 +4096,8 @@
   case Intrinsic::sadd_with_overflow: {
     SDValue Op1 = getValue(I.getOperand(1));
     SDValue Op2 = getValue(I.getOperand(2));
-    MVT Ty = Op1.getValueType();
 
-    MVT ValueVTs[] = { Ty, MVT::i1 };
+    MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
     SDValue Ops[] = { Op1, Op2 };
 
     SDValue Result =

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=59971&r1=59970&r2=59971&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 24 13:21:46 2008
@@ -780,6 +780,12 @@
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
+  // Add with overflow operations are custom lowered.
+  setOperationAction(ISD::SADDO, MVT::i32, Custom);
+  setOperationAction(ISD::SADDO, MVT::i64, Custom);
+  setOperationAction(ISD::UADDO, MVT::i32, Custom);
+  setOperationAction(ISD::UADDO, MVT::i64, Custom);
+
   // We have target-specific dag combine patterns for the following nodes:
   setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
   setTargetDAGCombine(ISD::BUILD_VECTOR);
@@ -6142,6 +6148,11 @@
   return Op;
 }
 
+SDValue X86TargetLowering::LowerXADDO(SDValue Op, SelectionDAG &DAG,
+                                      ISD::NodeType NTy) {
+  return SDValue();
+}
+
 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
   MVT T = Op.getValueType();
   unsigned Reg = 0;
@@ -6321,6 +6332,8 @@
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::CTLZ:               return LowerCTLZ(Op, DAG);
   case ISD::CTTZ:               return LowerCTTZ(Op, DAG);
+  case ISD::SADDO:              return LowerXADDO(Op, DAG, ISD::SADDO);
+  case ISD::UADDO:              return LowerXADDO(Op, DAG, ISD::UADDO);
       
   // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
   case ISD::READCYCLECOUNTER:

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=59971&r1=59970&r2=59971&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Nov 24 13:21:46 2008
@@ -592,6 +592,8 @@
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
     SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
     SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
+    SDValue LowerXADDO(SDValue Op, SelectionDAG &DAG, ISD::NodeType NTy);
+
     SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
     SDValue LowerATOMIC_BINARY_64(SDValue Op, SelectionDAG &DAG, 





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