[llvm-commits] [llvm] r59876 - /llvm/trunk/docs/WritingAnLLVMBackend.html

[Chris Lattner]

Author: lattner
Date: Sat Nov 22 13:10:48 2008
New Revision: 59876

URL: http://llvm.org/viewvc/llvm-project?rev=59876&view=rev
Log:
Describe how the JIT maps fields to MachineOperands, patch by
JP Bonn!

Modified:
    llvm/trunk/docs/WritingAnLLVMBackend.html

Modified: llvm/trunk/docs/WritingAnLLVMBackend.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=59876&r1=59875&r2=59876&view=diff

==============================================================================
--- llvm/trunk/docs/WritingAnLLVMBackend.html (original)
+++ llvm/trunk/docs/WritingAnLLVMBackend.html Sat Nov 22 13:10:48 2008
@@ -29,6 +29,7 @@
   </ul></li>
   <li><a href="#InstructionSet">Instruction Set</a>
   <ul>  
+    <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
     <li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
     <li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
   </ul></li>
@@ -998,6 +999,88 @@
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
+  <a name="operandMapping">Instruction Operand Mapping</a>
+</div>
+<div class="doc_text">
+<p>The code generator backend maps instruction operands to fields in
+the instruction.  Operands are assigned to unbound fields in the instruction in 
+the order they are defined. Fields are bound when they are assigned a value.
+For example, the Sparc target defines the XNORrr instruction as a F3_1 format 
+instruction having three operands.</p>
+</div>
+
+<div class="doc_code"> <pre>
+def XNORrr  : F3_1<2, 0b000111,
+                   (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+                   "xnor $b, $c, $dst",
+                   [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
+</pre></div>
+
+<div class="doc_text">
+<p>The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class for F3_1 is InstSP.</p>
+</div>
+
+<div class="doc_code"> <pre>
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+  field bits<32> Inst;
+  let Namespace = "SP";
+  bits<2> op;
+  let Inst{31-30} = op;       
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+InstSP leaves the op field unbound.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstSP<outs, ins, asmstr, pattern> {
+  bits<5> rd;
+  bits<6> op3;
+  bits<5> rs1;
+  let op{1} = 1;   // Op = 2 or 3
+  let Inst{29-25} = rd;
+  let Inst{24-19} = op3;
+  let Inst{18-14} = rs1;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3 binds the op field and defines the rd, op3, and rs1 fields.  F3 format instructions will
+bind the operands rd, op3, and rs1 fields.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+  bits<8> asi = 0; // asi not currently used
+  bits<5> rs2;
+  let op         = opVal;
+  let op3        = op3val;
+  let Inst{13}   = 0;     // i field = 0
+  let Inst{12-5} = asi;   // address space identifier
+  let Inst{4-0}  = rs2;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3_1 binds the op3 field and defines the rs2 fields.  F3_1 format instructions will
+bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction
+binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively.
+</p>
+</div>
+
+
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
   <a name="implementInstr">Implement a subclass of </a>
   <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
 </div>