[llvm-commits] [llvm] r59761 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAGInstrs.h include/llvm/Target/TargetInstrItineraries.h lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

[Evan Cheng]

On Nov 20, 2008, at 4:12 PM, Dan Gohman wrote:

>
> Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=59761&r1=59760&r2=59761&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Thu Nov  
> 20 18:12:10 2008
> @@ -73,6 +73,24 @@
>     unsigned StageIdx = Itineratries[ItinClassIndx].Last;
>     return Stages + StageIdx;
>   }
> +
> +  /// getLatency - Return the scheduling latency of the given  
> class.  A
> +  /// simple latency value for an instruction is an over- 
> simplification
> +  /// for some architectures, but it's a reasonable first  
> approximation.
> +  ///
> +  unsigned getLatency(unsigned ItinClassIndx) const {
> +    // If the target doesn't provide latency information, use a  
> simple
> +    // non-zero default value for all instructions.
> +    if (isEmpty())
> +      return 1;

Does it make sense for load instructions default latency to be 2?

Evan

>
> +
> +    // Just sum the cycle count for each stage.
> +    unsigned Latency = 0;
> +    for (const InstrStage *IS = begin(ItinClassIndx), *E =  
> end(ItinClassIndx);
> +         IS != E; ++IS)
> +      Latency += IS->Cycles;
> +    return Latency;
> +  }
> };
>
>
>
> Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=59761&r1=59760&r2=59761&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Nov 20 18:12:10  
> 2008
> @@ -50,7 +50,7 @@
>       assert(TRI->isPhysicalRegister(Reg) && "Virtual register  
> encountered!");
>       std::vector<SUnit *> &UseList = Uses[Reg];
>       SUnit *&Def = Defs[Reg];
> -      // Optionally add output and anti dependences
> +      // Optionally add output and anti dependences.
>       if (Def && Def != SU)
>         Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
>                      /*PhyReg=*/Reg, Cost);
> @@ -102,6 +102,15 @@
>   }
> }
>
> +void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
> +  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
> +
> +  // Compute the latency for the node.  We use the sum of the  
> latencies for
> +  // all nodes flagged together into this SUnit.
> +  SU->Latency =
> +    InstrItins.getLatency(SU->getInstr()->getDesc().getSchedClass());
> +}
> +
> void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
>   SU->getInstr()->dump();
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=59761&r1=59760&r2=59761&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu  
> Nov 20 18:12:10 2008
> @@ -193,15 +193,17 @@
>   }
>
>   SU->Latency = 0;
> -  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
> +  bool SawMachineOpcode = false;
> +  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
>     if (N->isMachineOpcode()) {
> -      unsigned SchedClass = TII->get(N- 
> >getMachineOpcode()).getSchedClass();
> -      const InstrStage *S = InstrItins.begin(SchedClass);
> -      const InstrStage *E = InstrItins.end(SchedClass);
> -      for (; S != E; ++S)
> -        SU->Latency += S->Cycles;
> +      SawMachineOpcode = true;
> +      SU->Latency +=
> +        InstrItins.getLatency(TII->get(N- 
> >getMachineOpcode()).getSchedClass());
>     }
> -  }
> +
> +  // Ensure that CopyToReg and similar nodes have a non-zero latency.
> +  if (!SawMachineOpcode)
> +    SU->Latency = 1;
> }
>
> /// CountResults - The results of target nodes have register or  
> immediate
>
>
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