[llvm-commits] [llvm] r59760 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Bill Wendling]

Author: void
Date: Thu Nov 20 18:11:16 2008
New Revision: 59760

URL: http://llvm.org/viewvc/llvm-project?rev=59760&view=rev
Log:
Add UADDO and SADDO nodes. These will be used for determining an overflow
condition in an addition operation.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=59760&r1=59759&r2=59760&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Nov 20 18:11:16 2008
@@ -249,7 +249,14 @@
     // to them to be chained together for add and sub of arbitrarily large
     // values.
     ADDE, SUBE,
-    
+
+    // Overflow-aware nodes for arithmetic operations. These nodes take two
+    // operands: the normal lhs and rhs to the add. They produce two results:
+    // the normal result of the add, and a flag indicating whether an overflow
+    // occured. These nodes are generated from the llvm.[su]add.with.overflow
+    // intrinsics. They are lowered by target-dependent code.
+    SADDO, UADDO,
+
     // Simple binary floating point operators.
     FADD, FSUB, FMUL, FDIV, FREM,
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=59760&r1=59759&r2=59760&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 20 18:11:16 2008
@@ -5151,6 +5151,8 @@
   case ISD::CARRY_FALSE:         return "carry_false";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
+  case ISD::SADDO:       return "saddo";
+  case ISD::UADDO:       return "uaddo";
   case ISD::SUBC:        return "subc";
   case ISD::SUBE:        return "sube";
   case ISD::SHL_PARTS:   return "shl_parts";