[llvm-commits] [llvm] r59734 - in /llvm/trunk/lib/Target/CellSPU: SPUAsmPrinter.cpp SPUISelLowering.cpp

[Scott Michel]

Author: pingbak
Date: Thu Nov 20 10:36:33 2008
New Revision: 59734

URL: http://llvm.org/viewvc/llvm-project?rev=59734&view=rev
Log:
CellSPU:
(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.

Removed:
    llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
Modified:
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp

Removed: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=59733&view=auto

==============================================================================
    (empty)

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=59734&r1=59733&r2=59734&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Nov 20 10:36:33 2008
@@ -130,15 +130,13 @@
   addRegisterClass(MVT::f64,  SPU::R64FPRegisterClass);
   addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
 
+  // Initialize libcalls:
+  setLibcallName(RTLIB::MUL_I64, "__muldi3");
+
   // SPU has no sign or zero extended loads for i1, i8, i16:
   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
-  setTruncStoreAction(MVT::i8,    MVT::i1, Custom);
-  setTruncStoreAction(MVT::i16,   MVT::i1, Custom);
-  setTruncStoreAction(MVT::i32,   MVT::i1, Custom);
-  setTruncStoreAction(MVT::i64,   MVT::i1, Custom);
-  setTruncStoreAction(MVT::i128,  MVT::i1, Custom);
 
   setLoadExtAction(ISD::EXTLOAD,  MVT::i8, Custom);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
@@ -212,6 +210,7 @@
   setOperationAction(ISD::ROTL, MVT::i32,    Legal);
   setOperationAction(ISD::ROTL, MVT::i16,    Legal);
   setOperationAction(ISD::ROTL, MVT::i8,     Custom);
+
   // SPU has no native version of shift left/right for i8
   setOperationAction(ISD::SHL,  MVT::i8,     Custom);
   setOperationAction(ISD::SRL,  MVT::i8,     Custom);
@@ -224,7 +223,7 @@
   // Custom lower i8, i32 and i64 multiplications
   setOperationAction(ISD::MUL,  MVT::i8,     Custom);
   setOperationAction(ISD::MUL,  MVT::i32,    Custom);
-  setOperationAction(ISD::MUL,  MVT::i64,    Custom);
+  setOperationAction(ISD::MUL,  MVT::i64,    Expand);
 
   // Need to custom handle (some) common i8, i64 math ops
   setOperationAction(ISD::ADD,  MVT::i64,    Custom);