[llvm-commits] [llvm] r59461 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

[Dan Gohman]

Author: djg
Date: Mon Nov 17 13:52:36 2008
New Revision: 59461

URL: http://llvm.org/viewvc/llvm-project?rev=59461&view=rev
Log:
Don't bother doing latency calculations in the "fast" scheduler.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=59461&r1=59460&r2=59461&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Nov 17 13:52:36 2008
@@ -139,12 +139,6 @@
 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
 void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain, 
                                   unsigned CurCycle) {
-  // FIXME: the distance between two nodes is not always == the predecessor's
-  // latency. For example, the reader can very well read the register written
-  // by the predecessor later than the issue cycle. It also depends on the
-  // interrupt model (drain vs. freeze).
-  PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
-
   --PredSU->NumSuccsLeft;
   
 #ifndef NDEBUG
@@ -277,7 +271,6 @@
     // FIXME: Calculate height / depth and propagate the changes?
     NewSU->Depth = SU->Depth;
     NewSU->Height = SU->Height;
-    ComputeLatency(NewSU);
 
     // LoadNode may already exist. This can happen when there is another
     // load from the same location and producing the same type of value
@@ -293,7 +286,6 @@
 
       LoadSU->Depth = SU->Depth;
       LoadSU->Height = SU->Height;
-      ComputeLatency(LoadSU);
     }
 
     SUnit *ChainPred = NULL;
@@ -530,13 +522,11 @@
     LRegsMap.clear();
     SUnit *CurSU = AvailableQueue.pop();
     while (CurSU) {
-      if (CurSU->CycleBound <= CurCycle) {
-        SmallVector<unsigned, 4> LRegs;
-        if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
-          break;
-        Delayed = true;
-        LRegsMap.insert(std::make_pair(CurSU, LRegs));
-      }
+      SmallVector<unsigned, 4> LRegs;
+      if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
+        break;
+      Delayed = true;
+      LRegsMap.insert(std::make_pair(CurSU, LRegs));
 
       CurSU->isPending = true;  // This SU is not in AvailableQueue right now.
       NotReady.push_back(CurSU);