[llvm-commits] [llvm] r59266 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86RegisterInfo.td
Chris Lattner
clattner at apple.com
Thu Nov 13 22:48:56 PST 2008
On Nov 13, 2008, at 1:52 PM, Dale Johannesen wrote:
> Author: johannes
> Date: Thu Nov 13 15:52:36 2008
> New Revision: 59266
>
> URL: http://llvm.org/viewvc/llvm-project?rev=59266&view=rev
> Log:
> Extend InlineAsm::C_Register to allow multiple specific registers
> (actually, code already all worked, only the comment
> changed). Use this to implement 'A' constraint on x86.
> Fixes PR 1779.
Hi Dale,
This is a very creative way to solve this problem. A couple questions:
> +// A class to support the 'A' assembler constraint: EAX then EDX.
> +def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
> + let MethodProtos = [{
> + iterator allocation_order_begin(const MachineFunction &MF) const;
> + iterator allocation_order_end(const MachineFunction &MF) const;
> + }];
> +
> + let MethodBodies = [{
> + static const unsigned X86_GRAD_AO[] = {X86::EAX, X86::EDX};
> + GRADClass::iterator
> + GRADClass::allocation_order_begin(const MachineFunction &MF)
> const {
> + return X86_GRAD_AO;
> + }
> +
> + GRADClass::iterator
> + GRADClass::allocation_order_end(const MachineFunction &MF)
> const {
> + return X86_GRAD_AO + (sizeof(X86_GRAD_AO) / sizeof(unsigned));
> + }
> + }];
> +}
> +
I think you can drop all the custom code and just have:
def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
The custom code is only needed when you don't want to be able to
allocate all regs from the class.
Did you measure the compile time impact of this? Does llc slow down
at "-O0" by adding another register class?
Finally, how does this fix the bug? Is isel still doing the 'register
allocation' of the 'A' constraint, or is it turning it into vregs from
the GRAD reg class? I thought the bug was that the isel regalloc was
assigning the tied register to EAX and then it just wasn't available
when handling the A constraint.
-Chris
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