[llvm-commits] [llvm] r59009 - in /llvm/trunk/lib/Target/CellSPU: SPUISelLowering.cpp SPUISelLowering.h SPUInstrInfo.td
Scott Michel
scottm at aero.org
Mon Nov 10 15:43:06 PST 2008
Author: pingbak
Date: Mon Nov 10 17:43:06 2008
New Revision: 59009
URL: http://llvm.org/viewvc/llvm-project?rev=59009&view=rev
Log:
CellSPU: Fix bug 3606, as well as some ongoing work.
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=59009&r1=59008&r2=59009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Nov 10 17:43:06 2008
@@ -978,7 +978,6 @@
case MVT::v8i16:
case MVT::v16i8:
ArgRegClass = &SPU::VECREGRegClass;
- ++ArgRegIdx;
break;
}
@@ -1034,7 +1033,7 @@
/// isLSAAddress - Return the immediate to use if the specified
/// value is representable as a LSA address.
static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
- ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+ ConstantSDNode *C = cast<ConstantSDNode>(Op);
if (!C) return 0;
int Addr = C->getZExtValue();
@@ -1148,7 +1147,7 @@
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
- if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+ if (GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
MVT CalleeVT = Callee.getValueType();
SDValue Zero = DAG.getConstant(0, PtrVT);
@@ -1173,7 +1172,7 @@
// address pairs:
Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero);
}
- } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
+ } else if (ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getExternalSymbol(S->getSymbol(), Callee.getValueType());
else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
// If this is an absolute destination address that appears to be a legal
@@ -1308,7 +1307,7 @@
}
if (OpVal.getNode() != 0) {
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
+ if (ConstantSDNode *CN = cast<ConstantSDNode>(OpVal)) {
return CN;
}
}
@@ -1462,9 +1461,9 @@
uint64_t EltUndefBits = ~0ULL >> (64-EltBitSize);
UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
continue;
- } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
+ } else if (ConstantSDNode *CN = cast<ConstantSDNode>(OpVal)) {
EltBits = CN->getZExtValue() & (~0ULL >> (64-EltBitSize));
- } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
+ } else if (ConstantFPSDNode *CN = cast<ConstantFPSDNode>(OpVal)) {
const APFloat &apf = CN->getValueAPF();
EltBits = (CN->getValueType(0) == MVT::f32
? FloatToBits(apf.convertToFloat())
@@ -2040,7 +2039,7 @@
SDValue N = Op.getOperand(0);
SDValue Elt = Op.getOperand(1);
SDValue ShufMask[16];
- ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt);
+ ConstantSDNode *C = cast<ConstantSDNode>(Elt);
assert(C != 0 && "LowerEXTRACT_VECTOR_ELT expecting constant SDNode");
@@ -2076,11 +2075,13 @@
prefslot_begin = 2; prefslot_end = 3;
break;
}
- case MVT::i32: {
+ case MVT::i32:
+ case MVT::f32: {
prefslot_begin = 0; prefslot_end = 3;
break;
}
- case MVT::i64: {
+ case MVT::i64:
+ case MVT::f64: {
prefslot_begin = 0; prefslot_end = 7;
break;
}
@@ -2704,6 +2705,28 @@
return SDValue();
}
+SDNode *SPUTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG)
+{
+#if 0
+ unsigned Opc = (unsigned) N->getOpcode();
+ MVT OpVT = N->getValueType(0);
+
+ switch (Opc) {
+ default: {
+ cerr << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
+ cerr << "Op.getOpcode() = " << Opc << "\n";
+ cerr << "*Op.getNode():\n";
+ N->dump();
+ abort();
+ /*NOTREACHED*/
+ }
+ }
+#endif
+
+ /* Otherwise, return unchanged */
+ return 0;
+}
+
//===----------------------------------------------------------------------===//
// Target Optimization Hooks
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=59009&r1=59008&r2=59009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Mon Nov 10 17:43:06 2008
@@ -111,9 +111,11 @@
/// getSetCCResultType - Return the ValueType for ISD::SETCC
virtual MVT getSetCCResultType(const SDValue &) const;
- /// LowerOperation - Provide custom lowering hooks for some operations.
- ///
+ //! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
+
+ //! Provide custom lowering hooks for nodes with illegal result types.
+ SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=59009&r1=59008&r2=59009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Mon Nov 10 17:43:06 2008
@@ -1372,6 +1372,13 @@
defm ORBI : BitwiseOrByteImm;
+// Truncate i16 -> i8
+def ORBItrunc : ORBIInst<(outs R8C:$rT), (ins R16C:$rA, u10imm:$val),
+ [/* empty */]>;
+
+def : Pat<(trunc R16C:$rSrc),
+ (ORBItrunc R16C:$rSrc, 0)>;
+
// OR halfword immediate
class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
@@ -1397,6 +1404,13 @@
defm ORHI : BitwiseOrHalfwordImm;
+// Truncate i32 -> i16
+def ORHItrunc : ORHIInst<(outs R16C:$rT), (ins R32C:$rA, u10imm:$val),
+ [/* empty */]>;
+
+def : Pat<(trunc R32C:$rSrc),
+ (ORHItrunc R32C:$rSrc, 0)>;
+
class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
IntegerOp, pattern>;
@@ -1431,6 +1445,13 @@
defm ORI : BitwiseOrImm;
+// Truncate i64 -> i32
+def ORItrunc : ORIInst<(outs R32C:$rT), (ins R64C:$rA, u10imm_i32:$val),
+ [/* empty */]>;
+
+def : Pat<(trunc R64C:$rSrc),
+ (ORItrunc R64C:$rSrc, 0)>;
+
// ORX: "or" across the vector: or's $rA's word slots leaving the result in
// $rT[0], slots 1-3 are zeroed.
//
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